Datasheet > 935336507518

935336507518

更新时间： 2024-09-22 07:33:59

品牌	Logo	应用领域
恩智浦 - NXP		微控制器
页数	文件大小	规格书
97页	2686K
描述
RISC Microcontroller

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935336507518 数据手册

LPC84x

32-bit Arm^®Cortex^®-M0+ microcontroller; up to 64 KB flash

and 16 KB SRAM; FAIM memory; 12-bit ADC; 10-bit DACs;

Comparator; Capacitive Touch Interface

Rev. 1.7 — 27 February 2018

Product data sheet

1. General description

The LPC84x are an Arm Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU

frequencies of up to 30 MHz. The LPC84x support up to 64 KB of flash memory and

16 KB of SRAM.

The peripheral complement of the LPC84x includes a CRC engine, four I²C-bus

interfaces, up to five USARTs, up to two SPI interfaces, Capacitive Touch Interface, one

multi-rate timer, self-wake-up timer, SCTimer/PWM, one general purpose 32-bit

counter/timer, a DMA, one 12-bit ADC, two 10-bit DACs, one analog comparator,

function-configurable I/O ports through a switch matrix, an input pattern match engine,

and up to 54 general-purpose I/O pins.

For additional documentation related to the LPC84x parts, see Section 18.

2. Features and benefits

 System:

 Arm Cortex-M0+ processor (revision r0p1), running at frequencies of up to 30 MHz

with single-cycle multiplier and fast single-cycle I/O port.

 Arm Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

 System tick timer.

 AHB multilayer matrix.

 Serial Wire Debug (SWD) with four break points and two watch points. JTAG

boundary scan (BSDL) supported.

 Micro Trace Buffer (MTB).

 Memory:

 Up to 64 KB on-chip flash programming memory with 64 Byte page write and

erase.

 Fast Initialization Memory (FAIM) allowing the user to configure chip behavior on

power-up.

 Code Read Protection (CRP)

 Up to 16 KB SRAM consisting of two 8 KB contiguous SRAM banks. One 8 KB of

SRAM can be used for MTB.

 Bit-band addressing supported to permit atomic operations to modify a single bit.

 ROM API support:

 Boot loader.

 Supports Flash In-Application Programming (IAP).

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