Datasheet > 935317935557

935317935557

更新时间： 2024-01-17 04:21:48

品牌	Logo	应用领域
恩智浦 - NXP		微控制器外围集成电路
页数	文件大小	规格书
76页	1316K
描述
Microcontroller

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技术参数
数据手册

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935317935557 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.66
uPs/uCs/外围集成电路类型：	MICROCONTROLLER	Base Number Matches：	1

935317935557 数据手册

Overview

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Bit reverse address mode, which effectively supports DSP and Fast Fourier

Transform algorithms

• Full shadowing of the register stack for zero-overhead context saves and restores:

nine shadow registers correspond to nine address registers (R0, R1, R2, R3, R4, R5,

N, N3, M01)

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions enable compact code

• Enhanced bit manipulation instruction set

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack, with the stack's depth limited only by

memory

• Priority level setting for interrupt levels

• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging

that is independent of processor speed

1.3 Operation Parameters

• Up to 50 MHz operation in normal mode and 100 MHz operation in fast mode

• Operation ambient temperature:

V Temperature option:-40 ^oC to 105^oC

M Temperature option:-40 ^oC to 125^oC

• Single 3.3 V power supply

• Supply range: V_DD- V_SS= 2.7 V to 3.6 V, V_DDA- V_SSA= 2.7 V to 3.6 V

1.4 On-Chip Memory and Memory Protection

• Dual Harvard architecture permits as many as three simultaneous accesses to

program and data memory

• Internal flash memory with security and protection to prevent unauthorized access

• Memory resource protection (MRP) unit to protect supervisor programs and

resources from user programs

• Programming code can reside in flash memory during flash programming

• The dual-port RAM controller supports concurrent instruction fetches and data

accesses, or dual data accesses by the core.

• Concurrent accesses provide increased performance.

• The data and instruction arrive at the core in the same cycle, reducing latency.

• On-chip memory

MC56F827xx, Rev. 4.1, 11/2018

NXP Semiconductors

1...3 4 567 8 9...76

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