Datasheet > 935310426557

935310426557

更新时间： 2023-02-26 13:20:50

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
147页	1781K
描述
Multifunction Peripheral

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935310426557 数据手册

•

Branch prediction with return stack

Low-interrupt latency

Instruction and data memory management units (MMUs), managed using micro TLB structures

backed by a unified main TLB

•

Instruction and data L1 caches, including a non-blocking data cache with hit-under-miss

Virtually indexed/physically addressed L1 caches

64-bit interface to both L1 caches

Write buffer (bypassable)

™

High-speed Advanced Micro Bus Architecture (AMBA) L2 interface

Vector floating point co-processor (VFP) for 3D graphics and hardware acceleration of other

floating-point applications

™

•

ETM and JTAG-based debug support

Table 3 summarizes information about the i.MX35 core.

Table 3. i.MX35 Core

Core

Acronym

Core

Name

Integrated Memory

Features

Brief Description

ARM11 or

ARM1136

ARM1136 The ARM1136™ platform consists of the ARM1136JF-S core, the ETM

• 16-Kbyte

Platform

real-time debug modules, a 6 × 5 multi-layer AHB crossbar switch (MAX), and

instruction cache

• 16-Kbyte data

cache

• 128-Kbyte L2

cache

a vector floating processor (VFP).

The i.MX35 provides a high-performance ARM11 microprocessor core and

highly integrated system functions. The ARM Application Processor (AP) and

other subsystems address the needs of the personal, wireless, and portable

product market with integrated peripherals, advanced processor core, and

power management capabilities.

• 32-Kbyte ROM

• 128-Kbyte RAM

2.5

Module Inventory

Table 4 shows an alphabetical listing of the modules in the MCIMX35. For extended descriptions of the

modules, see the MCIMX35 reference manual.

Table 4. Digital and Analog Modules

Block

Mnemonic

Block Name

Domain¹

Subsystem

Brief Description

1-WIRE 1-Wire

interface

ARM

ARM1136

platform

1-Wire provides the communication line to a 1-Kbit add-only

memory. the interface can send or receive 1 bit at a time.

peripherals

ASRC

Asynchronous SDMA

sample rate

converter

Connectivity

peripherals

The ASRC is designed to convert the sampling rate of a signal

associated to an input clock into a signal associated to a different

output clock. It supports a concurrent sample rate conversion of

about –120 dB THD+N. The sample rate conversion of each

channel is associated to a pair of incoming and outgoing sampling

rates.

i.MX35 Applications Processors for Automotive Products, Rev. 10

Freescale Semiconductor

1...4 5 678 9 10...147

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