8V19N492 Datasheet
Table 1. Pin Descriptions (Cont.)[a]
Pin
Name
Type[b]
Power
Description
67
31
VDD_INP
VDD_LCV1
VDD_LCV2
VDD_LCF
Positive supply voltage (3.3V) for the differential inputs (CLK0 to CLK1).
Positive supply voltage (3.3V) for internal VCXO_PLL circuits.
Positive supply voltage (3.3V) for internal VCXO_PLL circuits.
Positive supply voltage (3.3V) for the internal oscillator of the FemtoClockNG PLL.
Positive supply voltage (3.3V) for internal FemtoClockNG circuits.
Positive supply voltage (3.3V) for OSC, nOSC input and QCLKV, nQCLKV output.
Positive supply voltage (3.3V) for internal VCXO_PLL circuits.
Positive supply voltage (3.3V).
Power
Power
Power
Power
Power
Power
Power
34
39,40
43
VDD_CPF
VDD_QCLKV
VDD_CPV
VDD_SYNC
75, 80
74
30
Exposed
Pad (EP)
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
[a] See Section “Application Information” on page 67 for essential information on power supply filtering.
[b] PU (pull-up) and PD (pull-down) indicate internal input resistors (see Table 46 for values).
Principles of Operation
Overview
The 8V19N492 generates low-phase noise, synchronized clock and SYSREF output signals locked to an input reference frequency. The
device contains two PLLs with configurable frequency dividers. The first PLL (VCXO-PLL, suffix V) uses an external VCXO as the
oscillator and provides jitter attenuation. The external loop filter is used to set the VCXO-PLL bandwidth frequency in conjunction with
internal parameters. The second, low-phase noise PLL (FemtoClock NG, suffix F) multiplies the VCXO-PL1L frequency to 2949.12MHz.
The FemtoClock NG PLL is completely internal and provides a central timing reference point for all output signals. From this point, fully
synchronous dividers generate the output frequencies and the internal timing references for JESD204B support.
The device supports the generation of SYSREF pulses synchronous to the clock signals. There are five channels consisting of clock
and/or SYSREF outputs. The clock outputs are configurable with support for LVPECL or LVDS formats and a variable output amplitude.
Clock and SYSREF offer adjustable phase delay functionality. Individual outputs and channels and unused circuit blocks support
powered-down states for operating at lower power consumption. The register map, accessible through SPI interface with read-back
capability controls the main device settings and delivers device status information. For redundancy purpose, there are two selectable
reference frequency inputs and a configurable switch logic with priority-controlled auto-selection and holdover support.
©2022 Renesas Electronics Corporation
8
November 10, 2022
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