Radio Unit Clock Synchronizer and
Converter Clock Generator
8V19N850D
Datasheet
Description
Features
▪ High-performance radio clock synchronizer clock
The 8V19N850 is a fully integrated Radio Unit Clock Synchronizer and
Converter Clock Generator designed as a high-performance clock
solution for phase/frequency synchronization and signal conditioning of
wireless base station radio equipment. The device supports
JESD204B/C subclass 0 and 1 device clocks and SYSREF
synchronization for converters.
— Device clock domain (RF-PLL) with support for JESD204B/C
— Digital clock domain (Ethernet, FEC) with support for eEEC
and T-BC/T-TSC Class C
▪ 2 differential clock reference inputs
— 1PPS (1Hz) to 1GHz input frequency
The 8V19N850 supports two independent frequency domains: one that
can be used for the digital clock (Ethernet and FEC rates) domain with
four outputs, and the device clock (RF-PLL) domain with 12 outputs. The
Ethernet domain generates frequencies from two independent APLLs
for flexibility; the outputs of the RF clock domain generate very low
phase noise clocks for ADC/DAC circuits.
▪ Dual DPLL front-end with independent clock paths
— External control of the DCO for IEEE1588
— Digital holdover with a 1.1 × 10-7 ppb accuracy
— Programmable DPLL loop bandwidth 1mHz – 6kHz
— Configurable phase delay (range: 1UI)
From the integrated RF-PLL, the device supports the clock generation of
high-frequency device clocks for driving ADC/DAC devices
low-frequency synchronization signals (SYSREF).
— Hitless input switching with < 1ns output phase error
▪ Reference monitors for input LOS, activity and frequency
▪ 1 external synchronization input for JESD204B/C (LVCMOS)
▪ 16 differential outputs
▪ Dedicated phase management capabilities
▪ Optimized for low phase noise:
— Device clocks: -149.9dBc/Hz (1MHz offset; 245.76MHz clock)
▪ Supply voltage (core): 3.3V; (outputs): 3.3V, 2.5V, and 1.8V
▪ Package: 10 × 10 mm 88-VFQFPN
A dual DPLL front-end architecture supports any frequency translation.
Each DPLL provides a programmable bandwidth and a DCO function for
real-time frequency/phase adjustments. The DPLLs can lock on 1PPS
input signals and establish lock within 100s or less. Frequency
information can be applied from DPLL-0 to DPLL-1 and vice versa to
enable the combining of the frequency characteristics of two references
(combo-mode).
The 8V19N850 is configured through a pin-mapped I3CSM (including
legacy I2C) and 3/4-wire SPI interface. I2C with master capabilities
reads a default configuration from an external ROM device. GPIO ports
can be configured for reporting and controlling purposes.
▪ Board temperature range: -40°C to +105°C
Applicable Standards
▪ ITU-T G.8262 EEC1/2, G.8262.1 eEEC
▪ ITU-T G.8273.2 T-BC/T-TSC Class C
▪ JESD204B and C
Applications
▪ Wireless infrastructure 5G radio
Simplified Block Diagram
TCXO/OCXO
Clock 0
SYS_DPLL
4 Output Channels
Frequency Dividers
Phase Delay
4 Differential
Clock Outputs
≤1GHz
DPLL-0/APLL-0
APLL-2
RF-PLL
4
6 RF Output Channels
Clock + SYSREF
Frequency Dividers
Phase Delay
6 Differential
Clock Outputs
≤2.94912GHz
Clock 1
DPLL-1/APLL-1
Register
6
6
SYSREF
Generator
SYSREF
6 Differential
SYSREF Outputs
DCO Cmds
I3C/I2C/SPI
©2021–2023 Renesas Electronics Corporation
1
December 4, 2023
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