Datasheet > 8P391208NLGIW

8P391208NLGIW

更新时间： 2024-10-01 01:08:31

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
41页	919K
描述
Low Additive Jitter 2:8 Buffer with Universal Differential Outputs

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8P391208NLGIW 数据手册

Low Additive Jitter 2:8 Buffer with

Universal Differential Outputs

8P391208

Datasheet

General Description

Features

• Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS

reference clocks

8P391208 is intended to take 1 or 2 reference clocks, select

between them, using a pin selection and generate up to 8 outputs

that are the same as the reference frequency.

• Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz

(up to 1GHz when configured into HCSL output mode at 3.3V)

8P391208 supports two output banks, each with its own power

supply. All outputs in one bank would generate the same output

frequency, and each bank can be individually controlled for output

type or output enable.

• Select which of the two input clocks is to be used as the reference

clock for which bank via pin selection

• Generates 8 differential outputs

• Differential outputs selectable as LVPECL, LVDS, CML or HCSL

• CML mode supports two different voltage swings

The device can operate over the -40°C to +85°C temperature range.

• Differential outputs support frequencies from 1PPS to 700MHz

(up to 1GHz when configured into HCSL output mode at 3.3V)

• Outputs arranged in 2 banks of 4 outputs each

• Each bank supports a separate power supply of 3.3V, 2.5V or

1.8V

• Controlled by 3-level input pins

• Input mux selection control pin

• Control inputs are 3.3V-tolerant for all core voltages

• Output noise floor of -153dBc/Hz @ 156.25MHz

• Core voltage supply of 3.3V, 2.5V or 1.8V

• -40°C to +85°C ambient operating temperature

• Lead-free (RoHS 6) packaging

September 1, 2016

12 3 4 5 6 7...41

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