IDT8N4S270 Data Sheet
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Principles of Operation
Frequency Configuration
The block diagram consists of the internal 3rd overtone crystal and
oscillator which provide the reference clock fXTAL of either
An order code is assigned to each frequency configuration
programmed by the factory (default frequencies). For more
information on the available default frequencies and order codes,
please see the Ordering Information section in this document. For
available order codes, see the FemtoClock NG Ceramic-Package XO
and VCXO Ordering Product Information document.
114.285MHz or 100MHz. The PLL includes the FemtoClock NG
VCO along with the Pre-divider (P), the feedback divider (M) and the
post divider (N). The P, M, and N dividers determine the output fre-
quency based on the fXTAL reference. The feedback divider is frac-
For more information on programming capabilities of the device for
custom frequency and pull-range configurations, see the FemtoClock
NG Ceramic 5x7 Module Programming Guide.
tional supporting a huge number of output frequencies. The
configuration of the feedback divider to integer-only values results in
an improved output phase noise characteristics at the expense of
the range of output frequencies. Internal registers are used to hold
one factory pre-set P, M, and N configuration setting. The P, M, and
N frequency configuration supports an output frequency range from
15.476MHz to 866.67MHz and from 975MHz to 1,300MHz.
.
1
Table 3B. Output Frequency Range
15.476MHz to 866.67MHz
975MHz to 1,300MHz
The devices use the fractional feedback divider with a delta-sigma
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator.
1.
Supported output frequency range. The output frequency can
be programmed to any frequency in this range and to a precision of
218Hz or better.
The output frequency is determined by the 2-bit pre-divider (P), the
feedback divider (M) and the 7-bit post divider (N). The feedback
divider (M) consists of both a 7-bit integer portion (MINT) and an
18-bit fractional portion (MFRAC) and provides the means for
high-resolution frequency generation. The output frequency fOUT is
calculated by:
1
P N
MFRAC + 0.5
------------
-------------------------------------
f
= f
MINT +
OUT
XTAL
18
2
IDT8N4S270CCD REVISION A AUGUST 31, 2012
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©2012 Integrated Device Technology, Inc.