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88011216 PDF预览

88011216

更新时间: 2023-01-03 09:24:40
品牌 Logo 应用领域
京瓷/艾维克斯 - KYOCERA AVX /
页数 文件大小 规格书
21页 1027K
描述
Ceramic Capacitor, Multilayer, Ceramic, 500V, 10% +Tol, 10% -Tol, C0G, 30ppm/Cel TC, 0.27uF, Through Hole Mount, DIP

88011216 数据手册

 浏览型号88011216的Datasheet PDF文件第2页浏览型号88011216的Datasheet PDF文件第3页浏览型号88011216的Datasheet PDF文件第4页浏览型号88011216的Datasheet PDF文件第6页浏览型号88011216的Datasheet PDF文件第7页浏览型号88011216的Datasheet PDF文件第8页 
SMPS Stacked MLC Capacitors  
(SM Style) SM Military Styles MIL-PRF-49470/1  
MIL-PRF-49470/1  
MIL-PRF-49470/1 - capacitor, fixed, ceramic dielectric, switch mode power supply (general purpose and temperature stable),  
standard reliability and high reliability unencapsulated, Style PS01.  
D
E
A
See  
B
1.397 0.254  
(0.055 0.010)  
Note 4  
See  
Note 4  
SEATING PLANE  
6.35 (0.250) MIN  
See Note 3  
See Note 6  
0.254 0.05  
(0.010 0.002)  
2.54 (0.100) MAX  
0.635 (0.025) MIN  
(See Note 5)  
6.35 (0.250)  
MIN  
0.508 0.050  
(0.020 0.002)  
C
2.54 (0.100) TYP  
LEAD STYLE N AND A  
E
E
0.254 (0.010)  
RAD (TYP)  
0.254 (0.010)  
RAD (TYP)  
L
L
1.27 (0.050) MIN  
C
1.27 (0.050) MIN  
C
LEAD STYLE J AND C  
CIRCUIT DIAGRAM  
LEAD STYLE L AND B  
DIMENSIONS:  
millimeters (inches)  
D
Number of  
Leads  
per side  
Case Code  
C
0.ꢀ65 ( 0.0ꢁ5)  
E (max.)  
Min.  
Max.  
1
6
4
5
11.4 (0.450)  
ꢁ0.6 (0.800)  
11.4 (0.450)  
10.ꢁ (0.400)  
ꢀ.65 (0.ꢁ50)  
61.8 (1.ꢁ50)  
49.5 (1.950)  
6ꢀ.8 (1.450)  
ꢁ4.1 (0.950)  
8.89 (0.650)  
ꢀ.ꢁ0 (0.ꢁꢁ4)  
49.5 (1.950)  
5ꢁ.7 (ꢁ.075)  
40.0 (1.565)  
ꢁ7.6 (1.075)  
10.8 (0.4ꢁ5)  
ꢀ.97 (0.ꢁ75)  
5ꢁ.7 (ꢁ.075)  
1ꢁ.7 (0.500)  
ꢁꢁ.1 (0.870)  
1ꢁ.7 (0.500)  
11.ꢁ (0.440)  
7.ꢀꢁ (0.600)  
64.6 (1.650)  
ꢁ0  
15  
10  
4
6
ꢁ0  
NOTES:  
1. Dimensions are in millimeters (inches)  
2. Unless otherwise specified, tolerances are 0.254 ( 0.010).  
3. Lead frame configuration is shown as typical above the seating plane.  
4. See table I of MIL-PRF-49470/1 for specific maximum A dimension. For maximum B dimension, add 1.65 (0.065) to  
the appropriate A dimension. For all lead styles, the number of chips is determined by the capacitance and voltage  
rating.  
5. For case code 5, dimensions shall be 2.54 (0.100) maximum and 0.305 (0.012) minimum.  
6. Lead alignment within pin rows shall be within 0.10 (0.005).  
12  

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