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87946AYI-147LFT PDF预览

87946AYI-147LFT

更新时间: 2024-10-01 01:13:35
品牌 Logo 应用领域
艾迪悌 - IDT PC驱动逻辑集成电路
页数 文件大小 规格书
14页 211K
描述
1-to-10 Low Skew, LVCMOS/LVTTL Fanout Buffer

87946AYI-147LFT 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Lifetime Buy零件包装代码:TQFP
包装说明:LQFP, QFP32,.35SQ,32针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.28
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:11129766Samacsys Pin Count:32
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Quad Flat Packages
Samacsys Footprint Name:PRG32Samacsys Released Date:2020-01-31 03:45:19
Is Samacsys:N系列:87946
输入调节:MUXJESD-30 代码:S-PQFP-G32
JESD-609代码:e3长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:32实输出次数:10
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260电源:2.5/3.3 V
Prop。Delay @ Nom-Sup:5 ns传播延迟(tpd):5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.175 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmBase Number Matches:1

87946AYI-147LFT 数据手册

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1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL  
87946I-147  
Datasheet  
2.5V, 3.3V Fanout Buffer  
General Description  
Features  
The 87946I-147 is a low skew, ÷1, ÷2 LVCMOS/LVTTL Fanout  
Buffer. The 87946I-147 has two selectable single ended clock inputs.  
The single ended clock inputs accept LVCMOS or LVTTL input  
levels. The low impedance LVCMOS/LVTTL outputs are designed to  
drive 50series or parallel terminated transmission lines. The  
effective fanout can be increased from 10 to 20 by utilizing the ability  
of the outputs to drive two series terminated lines.  
Ten single ended LVCMOS/LVTTL outputs,  
7typical output impedance  
Selectable LVCMOS/LVTTL CLK0 and CLK1 inputs  
CLK0 and CLK1 can accept the following input levels:  
LVCMOS and LVTTL  
Maximum input frequency: 250MHz  
Bank skew: 30ps (maximum)  
The divide select inputs, DIV_SELx, control the output frequency of  
each bank. The outputs can be utilized in the ÷1, ÷2 or a combination  
of ÷1 and ÷2 modes. The master reset input, MR/nOE, resets the  
internal frequency dividers and also controls the active and high  
impedance states of all outputs.  
Output skew: 175ps (maximum)  
Part-to-part skew: 850ps (maximum)  
Multiple frequency skew: 200ps (maximum)  
3.3V core, 3.3V or 2.5V output supply modes  
-40°C to 85°C ambient operating temperature  
Lead-free packaging  
The 87946I-147 is characterized at full 3.3V for input VDD, and mixed  
3.3V and 2.5V for output operating supply mode. Guaranteed bank,  
output and part-to-part skew characteristics make the 87946I-147  
ideal for those clock distribution applications demanding well defined  
performance and repeatability.  
Block Diagram  
Pin Assignment  
Pulldown  
CLK_SEL  
Pullup  
CLK0  
CLK1  
0
1
0
1
÷1  
÷2  
3
QA[0:2]  
QB[0:2]  
32 31 30 29 28 27 26 25  
Pullup  
Pullup  
1
2
3
4
5
6
7
8
CLK_SEL  
GND  
24  
23  
22  
21  
20  
VDD  
QB0  
VDDB  
QB1  
GND  
Pulldown  
DIV_SELA  
CLK0  
0
1
CLK1  
3
DIV_SELA  
DIV_SELB  
DIV_SELC  
GND  
QB2  
VDDB  
VDDC  
19  
18  
17  
Pulldown  
DIV_SELB  
9
10 11 12 13 14 15 16  
0
1
4
QC[0:3]  
Pulldown  
Pulldown  
87946I-147  
DIV_SELC  
MR/nOE  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y Package  
Top View  
©2016 Integrated Device Technology, Inc.  
1
Revision C, September 19, 2016  

87946AYI-147LFT 替代型号

型号 品牌 替代类型 描述 数据表
87946AYI-147LF IDT

完全替代

1-to-10 Low Skew, LVCMOS/LVTTL Fanout Buffer

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