Datasheet > 87946I-147

87946I-147

更新时间： 2024-10-01 01:13:35

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
14页	211K
描述
1-to-10 Low Skew, LVCMOS/LVTTL Fanout Buffer

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87946I-147 数据手册

1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL

87946I-147

Datasheet

2.5V, 3.3V Fanout Buffer

General Description

Features

The 87946I-147 is a low skew, ÷1, ÷2 LVCMOS/LVTTL Fanout

Buffer. The 87946I-147 has two selectable single ended clock inputs.

The single ended clock inputs accept LVCMOS or LVTTL input

levels. The low impedance LVCMOS/LVTTL outputs are designed to

drive 50 series or parallel terminated transmission lines. The

effective fanout can be increased from 10 to 20 by utilizing the ability

of the outputs to drive two series terminated lines.

• Ten single ended LVCMOS/LVTTL outputs,

7 typical output impedance

• Selectable LVCMOS/LVTTL CLK0 and CLK1 inputs

• CLK0 and CLK1 can accept the following input levels:

LVCMOS and LVTTL

• Maximum input frequency: 250MHz

• Bank skew: 30ps (maximum)

The divide select inputs, DIV_SELx, control the output frequency of

each bank. The outputs can be utilized in the ÷1, ÷2 or a combination

of ÷1 and ÷2 modes. The master reset input, MR/nOE, resets the

internal frequency dividers and also controls the active and high

impedance states of all outputs.

• Output skew: 175ps (maximum)

• Part-to-part skew: 850ps (maximum)

• Multiple frequency skew: 200ps (maximum)

• 3.3V core, 3.3V or 2.5V output supply modes

• -40°C to 85°C ambient operating temperature

• Lead-free packaging

The 87946I-147 is characterized at full 3.3V for input V_DD,and mixed

3.3V and 2.5V for output operating supply mode. Guaranteed bank,

output and part-to-part skew characteristics make the 87946I-147

ideal for those clock distribution applications demanding well defined

performance and repeatability.

Block Diagram

Pin Assignment

Pulldown

CLK_SEL

Pullup

CLK0

CLK1

÷1

÷2

QA[0:2]

QB[0:2]

32 31 30 29 28 27 26 25

Pullup

CLK_SEL

GND

V^DD

QB0

VDDB

QB1

GND

Pulldown

DIV_SELA

CLK0

CLK1

DIV_SELA

DIV_SELB

DIV_SELC

GND

QB2

VDDB

VDDC

Pulldown

DIV_SELB

10 11 12 13 14 15 16

QC[0:3]

Pulldown

87946I-147

DIV_SELC

MR/nOE

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

Revision C, September 19, 2016

12 3 4 5 6 7...14

中文翻译

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与87946I-147相关器件

型号	品牌	获取价格	描述	数据表
87949AYI	IDT	获取价格	Low Skew Clock Driver, 87949 Series, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10 X
87949AYI-01	IDT	获取价格	Clock Driver, 87949 Series, 15 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.4
87949AYI-01T	IDT	获取价格	Clock Driver, 87949 Series, 15 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.4
87949AYI-147	IDT	获取价格	Clock Driver, PQFP52
87949AYI-147LFT	IDT	获取价格	Clock Driver, PQFP52
87949AYI-147T	IDT	获取价格	Clock Driver, PQFP52
87949AYILF	IDT	获取价格	TQFP-52, Tray
87949AYILFT	IDT	获取价格	TQFP-52, Reel
87949AYIT	IDT	获取价格	Low Skew Clock Driver, 87949 Series, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10 X
8795	INTEL	获取价格	COMMERCIAL/EXPRESS HMOS MICROCONTROLLER

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