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87946AYIT PDF预览

87946AYIT

更新时间: 2024-09-30 20:11:27
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
9页 1386K
描述
Low Skew Clock Driver, 87946 Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32

87946AYIT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32针数:32
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.49
系列:87946输入调节:MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.02 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:32实输出次数:10
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):240电源:3.3 V
Prop。Delay @ Nom-Sup:12 ns传播延迟(tpd):12 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.35 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:7 mmBase Number Matches:1

87946AYIT 数据手册

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ICS87946I  
Integrated  
Circuit  
Systems, Incꢀ  
LOW SKEW,  
÷1, ÷2  
LVCMOS CLOCK GENERATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS87946I is a low skew, ÷1, ÷2 LVCMOS  
• 10 single ended LVCMOS outputs, 7typical output  
,&6  
Clock Generator and a member of the  
HiPerClockS™ family of High Performance Clock  
Solutions from ICS. The ICS87946I has two select-  
able single ended clock inputs. The single ended  
impedance  
HiPerClockS™  
• Selectable CLK0 and CLK1 LVCMOS clock inputs  
• CLK0 and CLK1 can accept the following input levels:  
LVCMOS and LVTTL  
clock inputs accept LVCMOS or LVTTL input levels. The low  
impedance LVCMOS outputs are designed to drive 50series  
or parallel terminated transmission lines. The effective fanout  
can be increased from 10 to 20 by utilizing the ability of the  
outputs to drive two series terminated lines.  
• Maximum input/output frequency: 150MHz  
• Output skew: 350ps (maximum)  
• 3.3V input, 3.3V outputs  
The divide select inputs, DIV_SELx, control the output fre-  
quency of each bank. The outputs can be utilized in the ÷1,  
÷2 or a combination of ÷1 and ÷2 modes. The master reset  
input, MR/nOE, resets the internal frequency dividers and also  
controls the active and high impedance states of all outputs.  
• -40°C to 85°C ambient operating temperature  
• Pin compatible to the MPC946  
The ICS87946I is characterized at 3.3V core/3.3V output. Guar-  
anteed output and part-to-part skew characteristics make the  
ICS87946I ideal for those clock distribution applications demand-  
ing well defined performance and repeatability.  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
CLK_SEL  
0
1
CLK0  
0
1
÷1  
÷2  
QA0:QA2  
QB0:QB2  
QC0:QC3  
CLK1  
32 31 30 29 28 27 26 25  
CLK_SEL  
VDD  
DIV_SELA  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
GND  
QB0  
VDDB  
QB1  
GND  
QB2  
VDDB  
VDDC  
0
1
CLK0  
CLK1  
ICS87946I  
DIV_SELB  
DIV_SELA  
DIV_SELB  
DIV_SELC  
0
1
GND  
DIV_SELC  
MR/nOE  
9
10 11 12 13 14 15 16  
32-Lead LQFP  
7mm x 7mm x 1.4mm  
Y Package  
Top View  
87946AYI  
www.icst.com/products/hiperclocks.html  
REV. B OCTOBER 27, 2008  
1

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