Datasheet > 874003BG-05LF

874003BG-05LF

更新时间： 2024-01-25 10:19:23

品牌	Logo	应用领域
艾迪悌 - IDT		衰减器 PC
页数	文件大小	规格书
18页	803K
描述
PCI EXPRESS™ JITTER ATTENUATOR

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874003BG-05LF 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Lifetime Buy	零件包装代码：	TSSOP
包装说明：	6.50 X 4.40 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20	针数：	20
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.44
系列：	5V	输入调节：	STANDARD
JESD-30 代码：	R-PDSO-G20	JESD-609代码：	e3
长度：	6.5 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
湿度敏感等级：	1	功能数量：	1
反相输出次数：	3	端子数量：	20
实输出次数：	3	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.145 ns
座面最大高度：	1.2 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	4.4 mm
最小 fmax：	98 MHz	Base Number Matches：	1

874003BG-05LF 数据手册

ICS874003-05

PCI EXPRESS™ JITTER ATTENUATOR

Table 5. AC Characteristics, V_DD= V_DDO= 3.3V 5%, T_A= 0°C to 70°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f_MAX

Output Frequency

320

MHz

Cycle-to-Cycle Jitter;

NOTE 4

tjit(cc)

tsk(o)

tsk(b)

t_R/ t_F

odc

Output Skew; NOTE 4, 5

Bank Skew; NOTE 4, 6

Output Rise/Fall Time

Output Duty Cycle

145

Bank A

20% to 80%

200

600

100MHz output,

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

13.54

13.13

12.87

1.22

125MHz output,

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

Phase Jitter Peak-to-Peak;

NOTE 1, 3

t_j

250MHz output,

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

100MHz output,

High Band: 1.5MHz - Nyquist

(clock frequency/2)

125MHz output,

High Band: 1.5MHz - Nyquist

(clock frequency/2)

Phase Jitter RMS;

NOTE 2, 3

t_{REFCLK_HF_RMS}

1.17

250MHz output,

High Band: 1.5MHz - Nyquist

(clock frequency/2)

1.11

100MHz output,

Low Band: 10kHz - 1.5MHz

0.25

0.22

Phase Jitter RMS;

NOTE 2, 3

125MHz output,

Low Band: 10kHz - 1.5MHz

t_{REFCLK_LF_RMS}

250MHz output,

Low Band: 10kHz - 1.5MHz

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after

thermal equilibrium has been reached under these conditions.

NOTE 1: Peak-to-peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express

Gen 1 is 86ps peak-to-peak for a sample size of 10⁶clock periods. See IDT Application Note PCI Express Reference Clock

Requirements, and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall

composite transfer function.

NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and

reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for t_{REFCLK_HF_RMS}

(High Band) and 3.0 ps RMS for t_{REFCLK_LF_RMS}(Low Band). See IDT Application Note PCI Express Reference Clock Requirements and

also the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer

function.

NOTE 3: Guaranteed only when input clock source is PCI Express Gen 2 compliant.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross

points.

NOTE 6: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.

IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR

ICS874003BG-05 REV. A APRIL 15, 2009

1...3 4 567 8 9...18

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