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85C5121-ICSUL PDF预览

85C5121-ICSUL

更新时间: 2024-02-13 21:36:11
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟微控制器光电二极管外围集成电路
页数 文件大小 规格书
106页 691K
描述
Microcontroller, 8-Bit, 16MHz, CMOS, PDSO24, SSOP-24

85C5121-ICSUL 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:24
Reach Compliance Code:compliantHTS代码:8542.31.00.01
风险等级:5.84具有ADC:NO
地址总线宽度:位大小:8
最大时钟频率:16 MHzDAC 通道:NO
DMA 通道:NO外部数据总线宽度:
JESD-30 代码:R-PDSO-G24JESD-609代码:e3
长度:8.2 mm湿度敏感等级:3
I/O 线路数量:14端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
PWM 通道:NO封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.99 mm
速度:16 MHz最大供电电压:5.4 V
最小供电电压:2.85 V标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:5.29 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

85C5121-ICSUL 数据手册

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Table 1. Ports Description (Continued)  
Internal  
Power  
Signal  
Name  
Port  
Alternate  
Supply  
ESD  
Type Description  
EVCC  
VCC  
PWR Extra supply voltage  
EVCC is used to supply the level shifters of UART interface I/O  
pins. It must be connected to an external decoupling capacitor.  
This reference voltage is generated internally (automatically or not),  
or it can be connected to an external voltage reference.  
CVSS  
VSS  
GND DC/DC ground  
CVSS is used to sink high shunt currents from the external coil.  
GND Ground  
ONLY FOR PLCC52 version  
P0[7:0] AD[7:0]  
VCC  
I/O  
Input/Output function Port 0  
P0 is an 8-bit open-drain bi-directional I/O port. Port 0 pins that  
have 1s written to them float and can be used as high impedance  
inputs. To avoid any parasitic current consumption, Floating P0  
inputs must be pulled to VCC or VSS  
.
I/O  
I/O  
O
Address/Data low  
Mutiplexed Address/Data LSB for external access  
P2[7:0]  
A[15:8]  
VCC  
Input/Output function Port 2  
P2 is an 8-bit open-drain bi-directional I/O port with internal pull-ups  
Address high  
Address Bus MSB for external access  
P3.6  
P3.7  
ALE  
WR  
RD  
DVCC  
DVCC  
VCC  
O
Write signal  
Write signal asserted during external data memory write operation  
I
Read signal  
Read signal asserted during external data memory read operation  
O
Address latch enable output  
The falling edge of ALE strobes the address into external latch  
PSEN  
EA  
PSEN  
EA  
VCC  
VCC  
O
I
Program strobe enable  
External access enable  
This pin must be held low to force the device to fetch code from  
external program memory starting at address 0000h. It is latched  
during reset and cannot be dynamically changed during operation.  
8
T8xC5121  
4164B–8051–06/02  

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