Datasheet > 853S111AI

853S111AI

更新时间： 2022-02-26 12:18:03

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
20页	298K
描述
Differential-to-LVPECL/ECL Fanout Buffer

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Application Information

Wiring the Differential Input to Accept Single-Ended Levels

Figure 1 shows how a differential input can be wired to accept single

ended levels. The reference voltage V_REF= V_CC/2 is generated by

the bias resistors R1 and R2. The bypass capacitor (C1) is used to

help filter noise on the DC bias. This bias circuit should be located as

close to the input pin as possible. The ratio of R1 and R2 might need

to be adjusted to position the V_REFin the center of the input voltage

swing. For example, if the input clock swing is 2.5V and V_CC= 3.3V,

R1 and R2 value should be adjusted to set V_REFat 1.25V. The values

below are for when both the single ended swing and V_CCare at the

same voltage. This configuration requires that the sum of the output

impedance of the driver (Ro) and the series resistance (Rs) equals

the transmission line impedance. In addition, matched termination at

the input will attenuate the signal in half. This can be done in one of

two ways. First, R3 and R4 in parallel should equal the transmission

line impedance. For most 50 applications, R3 and R4 can be 100.

The values of the resistors can be increased to reduce the loading for

slower and weaker LVCMOS driver. When using single-ended

signaling, the noise rejection benefits of differential signaling are

reduced. Even though the differential input can handle full rail

LVCMOS signaling, it is recommended that the amplitude be

reduced. The datasheet specifies a lower differential amplitude,

however this only applies to differential signals. For single-ended

applications, the swing can be larger, however V_ILcannot be less

than -0.3V and V_IHcannot be more than V_CC+ 0.3V. Though some

of the recommended components might not be used, the pads

should be placed in the layout. They can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a differential signal.

Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT

BUFFER

Rev A 6/30/15

1...6 7 8910 11 12...20

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与853S111AI相关器件

型号	品牌	描述	获取价格	数据表
853S111AYILF	IDT	Differential-to-LVPECL/ECL Fanout Buffer	获取价格
853S111AYILFT	IDT	Differential-to-LVPECL/ECL Fanout Buffer	获取价格
853S111B	IDT	Low Skew, 1-to-10, Differential-to-2.5V, 3.3V LVPECL/ECL Fanout Buffer	获取价格
853S111B_16	IDT	Low Skew, 1-to-10, Differential-to-2.5V, 3.3V LVPECL/ECL Fanout Buffer	获取价格
853S111B_17	IDT	Low Skew Different ial-to-2 .5V, 3.3V LVPECL/ECL	获取价格
853S111BI	RENESAS	Low Skew, 1-to-10 Differential-to-2.5V, 3.3V LVPECL / ECL Fanout Buffer	获取价格