85105AGIT

更新时间： 2024-01-04 19:22:44

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	302K
描述
LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

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85105AGIT 数据手册

ICS85105I

LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both signals must meet the V_PP

and V_CMRinput requirements. Figures 3A to 3F show interface

examples for the HiPerClockS CLK/nCLK input driven by the

most common driver types.The input interfaces suggested here

are examples only. Please consult with the vendor of the driver

component to confirm the driver termination requirements. For

example in Figure 3A, the input termination applies for IDT

HiPerClockS open emitter LVHSTL drivers. If you are using an

LVHSTL driver from another vendor, use their termination

3.3V

1.8V

Zo = 50 Ohm

CLK

Zo = 50 Ohm

CLK

Zo = 50 Ohm

nCLK

Zo = 50 Ohm

HiPerClockS

LVPECL

Input

nCLK

HiPerClockS

LVHSTL

Input

ICS

HiPerClockS

LVHSTL Driver

FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY AN IDT OPEN EMITTER

FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 3.3V LVPECL DRIVER

HIPERCLOCKS LVHSTL DRIVER

3.3V

Zo = 50 Ohm

3.3V

125

LVDS_Driver

Zo = 50 Ohm

CLK

100

nCLK

Receiver

nCLK

HiPerClockS

Input

Zo = 50 Ohm

LVPECL

FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 3.3V LVPECL DRIVER

FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 3.3V LVDS DRIVER

2.5V

3.3V

2.5V

120

Zo = 50Ω

*R3

*R4

Zo = 60Ω

CLK

nCLK

HiPerClockS

Input

SSTL

HCSL

120

*Optional – R3 and R4 can be 0Ω

FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 2.5V SSTL DRIVER

FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 3.3V HCSL DRIVER

IDT^™/ ICS^™0.7V HCSL FANOUT BUFFER

ICS85105AGI REV. A JUNE 5, 2008

1...7 8 91011 12 13...16

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