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85102 PDF预览

85102

更新时间: 2024-02-26 12:43:34
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
17页 244K
描述
Low Skew, 1-to-2, Differential/LVCMOS HCSL Fanout Buffer

85102 技术参数

生命周期:TransferredReach Compliance Code:unknown
风险等级:5.27其他特性:STANDARD: MIL-C-26482, MAX CONTACTS (SERIES)=61
后壳类型:SOLID主体/外壳类型:RECEPTACLE
连接器类型:MIL SERIES CONNECTOR触点性别:FEMALE; MALE
耦合类型:BAYONETDIN 符合性:NO
空壳:NO环境特性:ENVIRONMENT/VIBRATION RESISTANT
滤波功能:NOIEC 符合性:NO
MIL 符合性:YES插接信息:MULTIPLE MATING PARTS AVAILABLE
混合触点:NO安装类型:PANEL
选件:GENERAL PURPOSE外壳面层:CADMIUM PLATED
外壳材料:ALUMINUM ALLOY外壳尺寸:8; 10; 12; 14; 16; 18; 20; 22; 24
端接类型:SOLDERBase Number Matches:1

85102 数据手册

 浏览型号85102的Datasheet PDF文件第2页浏览型号85102的Datasheet PDF文件第3页浏览型号85102的Datasheet PDF文件第4页浏览型号85102的Datasheet PDF文件第6页浏览型号85102的Datasheet PDF文件第7页浏览型号85102的Datasheet PDF文件第8页 
85102 DATA SHEET  
TABLE 5. AC CHARACTERISTICS, V = 3.3V 10ꢀ, TA = -40°C TO 85°C  
DD  
Symbol Parameter  
Test Conditions  
Minimum Typical Maximum Units  
CLK_SEL = 0  
CLK_SEL = 1  
CLK_SEL = 0  
CLK_SEL = 1  
500  
250  
3.2  
2.8  
65  
MHz  
MHz  
ns  
f
t
Output Frequency  
OUT  
PD  
2.0  
2.0  
Propagation Delay; NOTE 1  
ns  
tsk(o)  
Output Skew; NOTE 2, 4  
ps  
tsk(pp)  
Part-to-Part Skew; NOTE 3, 4  
600  
ps  
100MHz (12kHz - 20MHz)  
250MHz (12kHz - 20MHz)  
0.22  
0.14  
ps  
Buffer Additive Phase Jitter, RMS;  
refer to Additive Phase Jitter Section  
tjit  
ps  
Absolute Maximum Output Voltage; NOTE  
5, 10  
V
1150  
100  
mV  
mV  
MAX  
Absolute Minimum Output Voltage;  
NOTE 5, 11  
V
-300  
MIN  
V
Ringback Voltage; NOTE 6, 13  
-100  
500  
250  
mV  
ps  
RB  
t
Time before V is allowed; NOTE 6, 13  
STABLE  
RB  
V
Absolute Crossing Voltage; NOTE 5, 8, 9  
550  
140  
mV  
CROSS  
Total Variation of V  
NOTE 5, 8, 12  
over all edges;  
CROSS  
DV  
mV  
CROSS  
Measured between  
-150mV to +150mV  
Rise/Fall Edge Rate; NOTE 6, 7  
0.6  
45  
5.5  
55  
V/ns  
odc  
Output Duty Cycle; NOTE 14  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the  
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after  
thermal equilibrium has been reached under these conditions.  
NOTE: All parameters measured at ƒout £ 250MHz unless noted otherwise.  
NOTE 1: Measured from the V /2 of the input to the differential output crossing point.  
DD  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differ-  
ential cross points.  
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, and with  
equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.  
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 5: Measurement taken from single-ended waveform.  
NOTE 6: Measurement taken from differential waveform.  
NOTE 7: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic  
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.  
See Parameter Measurement Information Section.  
NOTE 8: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.  
See Parameter Measurement Information Section.  
NOTE 9: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all  
crossing points for this measurement. See Parameter Measurement Information Section.  
NOTE 10: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.  
NOTE 11: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.  
NOTE 12: Defined as the total variation of all crossing voltage of Rising Qx and Falling nQx. This is the maximum allowed variance in  
the V  
for any particular system. See Parameter Measurement Information Section.  
CROSS  
NOTE: 13. T  
is the time the differential clock must maintain a minimum 150mV differential voltage after rising/falling edges before  
it is allowed StoTABLdEroop back into the V 100mV differential range. See Parameter Measurement Information Section.  
RB  
NOTE 14: Input duty cycle must be 50ꢀ.  
REVISION B 12/19/14  
5
Low Skew, 1-to-2, Differential/LVCMOS-to-0.7V HCSL  
Fanout Buffer  

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