Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
84C44X; 84C64X; 84C84X
7
RESET
7.1
Power-on-reset
The RESET pin (active LOW input) is used to initialize the
microcontroller to a defined state. The Reset configuration
is shown in Fig.5.
The Power-on-reset circuit monitors the voltage level of
VDD. If VDD remains below the internal reference voltage
level Vref (typically 1.3 V), the oscillator is inhibited.
When VDD rises above Vref, the oscillator is released and
the internal reset is active for a period of td (typically
50 µs).
Considering the VDD rise time, the following measures for
a correct Power-on-reset can be taken:
V
DD
handbook, halfpage
• If the VDD rises above the minimum operation voltage
before time period td is exceeded, no external
components are necessary (see Fig.6).
R
100 kΩ
RESET
• If VDD has a slow rise time, such that after the time
period(tVref + td) has elapsed the supply voltage is still
below the minimum operation voltage (Vmin),
C
external components are required (see Figs 4 and 7).
To guarantee a correct reset operation, ensure that
V
SS
MCD174
the time constant RC ≥ 8 × tVDD
.
A definite Power-on-reset can be realized by applying an
(external) RESET signal during power-on.
Fig.4 External components for RESET pin.
handbook, full pagewidth
V
DD
oscillator
inhibit
POWER
ON
RESET
V
ref
RESET
internal
reset
V
SS
MLA651
Fig.5 Reset configuration.
October 1994
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