PRELIMINARY
ICS84330-01
Integrated
Circuit
Systems, Inc.
700MHZ, LOW
J
ITTER, CRYSTAL
-TO-3.3V
D
IFFERENTIAL LVPECL FREQUENCY YNTHESIZER
S
TABLE 1. PIN DESCRIPTIONS
Name
Type
Description
Core supply pins.
VCC
Power
Power
Power
Power
VCCA
Analog supply pin for the PLL.
Negative supply pins.
Output supply pin.
VEE
VCCO
nc
Unused
Input
Do not connect.
XTAL1, XTAL2
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Parallel load input. Determines when data present at M8:M0 is loaded into
M divider, and when data present at N1:N0 sets the N output divide value.
LVCMOS / LVTTL interface levels.
nP_LOAD
Input
Pullup
Clocks the serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the M divider.
LVCMOS / LVTTL interface levels.
S_CLOCK
S_DATA
Input
Input
Input
Pulldown
Pulldown
Pulldown
S_LOAD
M0, M1, M2
M3, M4, M5
M6, M7, M8
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
LVCMOS / LVTTL interface levels.
Input
Input
Pullup
Pullup
Determines N output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
N0, N1
Test output which is used in the serial mode of operation.
LVCMOS / LVTTL interface levels.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
TEST
Output
Output
nFOUT, FOUT
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
84330BV-01
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 18, 2003
3