Datasheet > 843002BKI-72LF

843002BKI-72LF

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
艾迪悌 - IDT		时钟发生器石英晶振压控振荡器衰减器
页数	文件大小	规格书
18页	296K
描述
FEMTOCLOCKS⑩ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR

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843002BKI-72LF 数据手册

FEMTOCLOCKS™ VCXO BASED WCDMA

CLOCK GENERATOR/JITTER ATTENUATOR

ICS843002I-72

GENERAL DESCRIPTION

FEATURES

The ICS843002I-72 is

ICS

member of the

• Two differential LVPECL outputs

HiperClockS™ family of high performance clock

solutions from IDT. The ICS843002I-72 is a

PLL based synchronous clock generator that is

optimized for WCDMA channel card applications

• CLK input accepts the following input levels:

LVCMOS or LVTTL levels

HiPerClockS™

• Output frequency: 122.88MHz (typical)

where jitter attenuation and frequency translation is needed.

The device contains two internal PLL stages that are cascaded

in series. The first PLL stage uses a VCXO which is optimized

to provide reference clock jitter attenuation and to be jitter

tolerant, and to provide a stable reference clock for the second

PLL stage.The second PLL stage provides additional frequency

multiplication (x32), and it maintains low output jitter by using a

low phase noise FemtoClock™VCO. The device performance

and the PLL multiplication ratios are optimized to support

WCDMA applications. The VCXO requires the use of an

external, inexpensive pullable crystal. VCXO PLL uses external

passive loop filter components which are used to optimize the

PLL loop bandwidth and damping characteristics for the given

application.

• FemtoClock VCO frequency range: 490MHz - 680MHz

• RMS phase jitter @ 122.88MHz, using a 19.2MHz crystal

(1.875MHz to 10MHz): 0.49ps (typical)

• Deterministic jitter: 30fs (typical)

• Random jitter, RMS: 2.2ps (typical)

• Full 3.3V or mixed 3.3V core/2.5V output supply voltage

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

The ICS843002I-72 can accept a single-ended input. LOCK_DT

reports the lock status of VCXO PLL loop. If the reference clock

input is lost, it will set LOCK_DT to logic LOW.

Typical ICS843002I-72 configuration in WCDMA Systems:

• 19.2MHz pullable crystal

• Input Reference clock frequency: 3.84MHz

• Output clock frequency: 122.88MHz

PIN ASSIGNMENT

32 31 30 29 28 27 26 25

LF1

LF0

ISET

V^CC

LOCK_DT

V^EE

VCC

VCCO

nQ1

VCC

VEE

CLK

V^EE

10 11 12 13 14 15 16

ICS843002I-72

32-Lead VFQFN

5mm x 5mm x 0.925 package body

K Package

Top View

IDT^™/ ICS^™WCDMA CLOCK GENERATOR/JITTER ATTENUATOR

ICS843002BKI-72 REV. A NOVEMBER 21, 2007

12 3 4 5 6 7...18

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