Datasheet > 841S01BGI

841S01BGI

更新时间： 2024-01-29 15:51:14

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
13页	271K
描述
Clock Generator

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

841S01BGI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.92
Base Number Matches：	1

841S01BGI 数据手册

PRELIMINARY

ICS841S01I

Integrated

Circuit

Systems, Inc.

PCI EXPRESS™ CLOCK GENERATOR

SERIAL DATA INTERFACE

DATA PROTOCOL

To enhance the flexibility and function of the clock synthe-

sizer, a two-signal serial interface is provided. Through the

Serial Data Interface, various device functions, such as

individual clock output buffers, can be individually enabled

or disabled. The registers associated with the Serial Data

Interface initialize to their default setting upon power-up,

and therefore, use of this interface is optional. Clock device

ization, if any are required. The interface cannot be used

during system operation for power management functions.

The clock driver serial protocol accepts byte write, byte

read, block write, and block read operations from the con-

troller. For block write/read operation, the bytes must be

accessed in sequential order from lowest to highest byte

(most significant bit first) with the ability to stop after any

complete byte has been transferred. For byte write and byte

read operations, the system controller can access individu-

ally indexed bytes. The offset of the indexed byte is en-

coded in the command code, as described in Table 3A.

The block write and block read protocol is outlined in Table

3B, while Table 3C outlines the corresponding byte write

and byte read protocol. The slave receiver address is

11010010 (D2h).

TABLE 3A. COMMAND CODE DEFINITION

BIT

Description

0 = Block read or block write operation, 1 = Byte read or byte write operation.

Chip select address, set to "00" to access device.

6:5

Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be

"00000".

4:0

TABLE 3B. BLOCK READ AND BLOCKWRITE PROTOCOL

BIT

Description = Block Write

Start

BIT

Description = Block Read

Start

2:8

Slave address - 7 bits

Write

2:8

Slave address - 7 bits

Write

Acknowledge from slave

11:18 Command Code - 8 bits

19 Acknowledge from slave

20:27 Byte Count - 8 bits

28 Acknowledge from slave

29:36 Data byte 1 - 8 bits

37 Acknowledge from slave

38:45 Data byte 2 - 8 bits

11:18 Command Code - 8 bits

Acknowledge from slave

Repeat start

21:27 Slave address - 7 bits

Read = 1

Acknowledge from slave

30:37 Byte Count from slave - 8 bits

38 Acknowledge

39:46 Data Byte 1 from slave - 8 bits

47 Acknowledge

48:55 Data Byte 2 from slave - 8 bits

Acknowledge from slave

Data Byte/Slave Acknowledges

Data Byte N - 8 bits

Acknowledge from slave

Stop

Acknowledge

Data Bytes from Slave / Acknowledges

Data Byte N from slave - 8 bits

Not Acknowledge

841S01BGI

www.icst.com/products/hiperclocks.html

JUNE 12, 2006

1 234 5 6 7...13

下载PDF

与841S01BGI相关器件

型号	品牌	描述	获取价格	数据表
841S01BGILF	IDT	Clock Generator	获取价格
841S01BGILFT	IDT	Clock Generator	获取价格
841S01BGIT	IDT	Clock Generator	获取价格
841S01CG	IDT	Processor Specific Clock Generator, 100MHz, CMOS, PDSO16, 4.40 X 5 MM, 0.925 MM HEIGHT, MO	获取价格
841S01CGT	IDT	Processor Specific Clock Generator, 100MHz, CMOS, PDSO16, 4.40 X 5 MM, 0.925 MM HEIGHT, MO	获取价格
841S02BGI	IDT	Clock Generator	获取价格