Datasheet > 841N4830BKILFT

841N4830BKILFT

更新时间： 2024-01-21 14:50:16

品牌	Logo	应用领域
艾迪悌 - IDT		时钟外围集成电路晶体
页数	文件大小	规格书
28页	491K
描述
FemtoClock NG Crystal-to-HCSL Frequency Synthesizer

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841N4830BKILFT 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	VFQFPN
包装说明：	HVQCCN,	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.76
JESD-30 代码：	S-XQCC-N32	JESD-609代码：	e3
长度：	5 mm	湿度敏感等级：	3
端子数量：	32	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出时钟频率：	100 MHz
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	主时钟/晶体标称频率：	25 MHz
座面最大高度：	1 mm	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	5 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

841N4830BKILFT 数据手册

841N4830 Datasheet

Table 6C. HCSL AC Characteristics, V = 3.0V to 3.6V, V

= 2.7V to 3.6V, T = -40°C to 85°C

DDO

Symbol

Parameter

Test Conditions

PLL

Minimum

Typical

Maximum

Units

MHz

100

f_OUT

Output Frequency

PLL Bypass

f_REF

Reference Frequency

tsk(b)

Bank Skew; NOTE 1, 10

Phase Jitter, RMS (Random);

NOTE 11

100MHz, Integration Range:

12kHz – 20MHz

tjit(Ø)

0.36

100MHz, 25MHz crystal input

High Band: 1.5MHz - Nyquist

(clock frequency/2)

t_{REFCLK_HF_RMS}Phase Jitter RMS; NOTE 2

t_{REFCLK_LF_RMS}Phase Jitter RMS; NOTE 2

0.600

0.023

100MHz, 25MHz crystal input

Low Band: 10kHz - 1.5MHz

tjit(cc)

Cycle-to-Cycle Jitter

PLL Lock Time

PLL Mode

t_L

Ring-back Voltage Margin;

NOTE 4, 9

V_RB

-100

500

100

Time before V_RBis allowed;

NOTE 4, 9

t_STABLE

V_HIGH

V_LOW

Voltage High

Voltage Low

520

920

150

-150

Absolute Crossing Voltage;

NOTE 3, 6, 7

V_CROSS

160

460

140

Total Variation of V_CROSSover

all edges; NOTE 3, 6, 8

V_CROSS

Rising Edge Rate; NOTE 4, 5

Falling Edge Rate; NOTE 4, 5

0.6

4.0

V/ns

Power Supply Noise

Reduction

PSNR

odc

-45

Output Duty Cycle; NOTE 4

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.

NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and

reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t_{REFCLK_HF_RMS}

(High Band) and 3.0ps RMS for t_{REFCLK_LF_RMS}(Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also

the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.

NOTE 3: Measurement taken from single ended waveform.

NOTE 4: Measurement taken from differential waveform.

NOTE 5: Measured from -150mV to +150mV on the differential waveform (derived from Q minus nQ). The signal must be monotonic through

the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

NOTE 6: Measured at the crosspoint where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ.

NOTE 7: Refers to the total variation from the lowest crosspoint to the highest, regardless of which edge is crossing. Refers to all crosspoints

for this measurement.

NOTE 8: Defined as the total variation of all crossing voltages of rising Q and falling nQ, This is the maximum allowed variance in V_CROSSfor

any particular system.

NOTE 9: T_STABLEis the time the differential clock must maintain a minimum 150mV differential voltage after rising/falling edges before it is

allowed to drop back into the V_RB100mV differential range.

NOTE 10: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 11: See Phase Noise Plot.

Revision F, May 23, 2016

1...4 5 678 9 10...28

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