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83C51FC-33 PDF预览

83C51FC-33

更新时间: 2022-12-01 20:01:58
品牌 Logo 应用领域
英特尔 - INTEL 微控制器
页数 文件大小 规格书
20页 241K
描述
Microcontroller,

83C51FC-33 数据手册

 浏览型号83C51FC-33的Datasheet PDF文件第6页浏览型号83C51FC-33的Datasheet PDF文件第7页浏览型号83C51FC-33的Datasheet PDF文件第8页浏览型号83C51FC-33的Datasheet PDF文件第10页浏览型号83C51FC-33的Datasheet PDF文件第11页浏览型号83C51FC-33的Datasheet PDF文件第12页 
8XC51FX  
DC CHARACTERISTICS (Over Operating Conditions)  
All parameter values apply to all devices unless otherwise indicated. (Continued)  
Typical  
(Note 4)  
Symbol  
Parameter  
Min  
Max  
Units  
Test Conditions  
e
g
I
I
Input leakage Current (Port 0)  
10  
mA  
V
V
V or V  
IL IH  
LI  
IN  
e
Logical 1 to 0 Transition Current  
(Ports 1, 2 and 3)  
Express  
2V  
TL  
IN  
b
b
750  
650  
mA  
Commercial  
RRST  
CIO  
RST Pulldown Resistor  
Pin Capacitance  
40  
225  
KX  
@
1MHz, 25 C  
10  
pF  
§
I
Power Supply Current:  
Active Mode  
(Note 3)  
CC  
At 12 MHz (Figure 5)  
At 16 MHz  
At 24 MHz  
At 33 MHz  
Idle Mode  
15  
20  
28  
35  
30  
38  
56  
56  
mA  
mA  
mA  
mA  
At 12 MHz (Figure 5)  
At 16 MHz  
At 24 MHz  
At 33 MHz  
Power Down Mode  
5
6
7
7
5
7.5  
9.5  
13.5  
15  
mA  
mA  
mA  
mA  
mA  
75  
NOTES:  
1. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the V s of ALE and  
OL  
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins  
change from 1 to 0. In applications where capacitance loading exceeds 100 pF, the noise pulses on these signals may  
exceed 0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic.  
2. Capacitive loading on Ports 0 and 2 cause the V  
address lines are stabilizing.  
on ALE and PSEN to drop below the 0.9 V specification when the  
CC  
OH  
3. See Figures 6–9 for test conditions. Minimum V  
for power down is 2V.  
CC  
4. Typicals are based on limited number of samples, and are not guaranteed. The values listed are at room temperature and 5V.  
5. Under steady state (non-transient) conditions, I must be externally limited as follows:  
OL  
Maximum I per port pin:  
OL  
10 mA  
Maximum I per 8-bit port -  
OL  
Port 0:  
Ports 1, 2, and 3:  
Maximum total I for all output pins:  
26 mA  
15 mA  
71 mA  
OL  
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater  
OL OL  
than the listed test conditions.  
272322–5  
Note:  
I
g
g
max at 24 MHz and below is at 5V 20% V  
max at 33 MHz is at 5V 10% V , while I  
CC  
.
CC  
CC  
CC  
Figure 5. 8XC51FA/FB/FC I vs Frequency  
CC  
9

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