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830154BMI-09LF PDF预览

830154BMI-09LF

更新时间: 2024-01-31 21:46:59
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
14页 806K
描述
SOIC-8, Tube

830154BMI-09LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:3.90 X 4.90 MM, 1.375 MM HEIGHT, ROHS COMPLIANT, MS-012, SOIC-8针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
系列:830154输入调节:STANDARD
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.004 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:8实输出次数:4
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:1.5/1.8 V
Prop。Delay @ Nom-Sup:4.1 ns传播延迟(tpd):4.1 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.04 ns
座面最大高度:1.75 mm子类别:Clock Drivers
最大供电电压 (Vsup):1.6 V最小供电电压 (Vsup):1.4 V
标称供电电压 (Vsup):1.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

830154BMI-09LF 数据手册

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ICS830154I-09 Data Sheet  
OVER-VOLTAGE 1.5V TOLERANT, 1:4 FANOUT BUFFER  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the fundamental  
compared to the power of the fundamental is called the dBc Phase  
Noise. This value is normally expressed using a Phase noise plot  
and is most often the specified plot in many applications. Phase noise  
is defined as the ratio of the noise power present in a 1Hz band at a  
specified offset from the fundamental frequency to the power value of  
the fundamental. This ratio is expressed in decibels (dBm) or a ratio  
of the power in the 1Hz band to the power in the fundamental. When  
the required offset is specified, the phase noise is called a dBc value,  
which simply means dBm at a specified offset from the fundamental.  
By investigating jitter in the frequency domain, we get a better  
understanding of its effects on the desired application over the entire  
time record of the signal. It is mathematically possible to calculate an  
expected bit error rate given a phase noise plot.  
Additive Phase Jitter @ 25MHz  
12kHz to 5MHz = 0.241ps (typical)  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements has  
issues relating to the limitations of the equipment. Often the noise  
floor of the equipment is higher than the noise floor of the device. This  
is illustrated above. The device meets the noise floor of what is  
shown, but can actually be lower. The phase noise is dependent on  
the input source and measurement equipment.  
The source generator "IFR2042 10kHz – 56.4GHz Low Noise Signal  
Generator as external input to an Agilent 8133A 3GHz Pulse  
Generator".  
ICS830154BGI-09 REVISION A JUNE 9, 2010  
6
©2010 Integrated Device Technology, Inc.  

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