Datasheet > 82V3280DQG

82V3280DQG

更新时间： 2024-02-14 02:08:07

品牌	Logo	应用领域
艾迪悌 - IDT		电信电信集成电路
页数	文件大小	规格书
167页	1465K
描述
Telecom Circuit, 1-Func, CMOS, PQFP100, GREEN, TQFP-100

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

82V3280DQG 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	GREEN, TQFP-100
针数：	100	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.14
JESD-30 代码：	S-PQFP-G100	JESD-609代码：	e3
长度：	14 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	1.6 mm	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

82V3280DQG 数据手册

WAN PLL

IDT82V3280

•

Supports automatic hitless selected input clock switch on clock fail-

ure

Supports three types of input clock sources: recovered clock from

STM-N or OC-n, PDH network synchronization timing and external

synchronization reference timing

FEATURES

HIGHLIGHTS

•

The first single PLL chip:

• Features 0.5 mHz to 560 Hz bandwidth

• Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/

Option I) jitter generation requirements

• Provides node clocks for Cellular and WLL base-station (GSM

and 3G networks)

• Provides clocks for DSL access concentrators (DSLAM), espe-

cially for Japan TCM-ISDN network timing based ADSL equip-

ments

•

Provides a 2 kHz, 4 kHz or 8 kHz frame sync input signal, and a 2

kHz and an 8 kHz frame sync output signals

Provides 14 input clocks whose frequency cover from 2 kHz to

622.08 MHz

Provides 9 output clocks whose frequency cover from 1 Hz to

622.08 MHz

Provides output clocks for BITS, GPS, 3G, GSM, etc.

Supports AMI, PECL/LVDS and CMOS input/output technologies

Supports master clock calibration

Supports Master/Slave application (two chips used together) to

enable system protection against single chip failure

Meets Telcordia GR-1244-CORE, GR-253-CORE, GR-1377-

CORE, ITU-T G.812, ITU-T G.813 and ITU-T G.783 criteria

•

MAIN FEATURES

•

Provides an integrated single-chip solution for Synchronous Equip-

ment Timing Source, including Stratum 2, 3E, 3, SMC, 4E and 4

clocks

•

Employs DPLL and APLL to feature excellent jitter performance

and minimize the number of the external components

Integrates T0 DPLL and T4 DPLL; T4 DPLL locks independently or

locks to T0 DPLL

Supports Forced or Automatic operating mode switch controlled by

an internal state machine; the primary operating modes are Free-

Run, Locked and Holdover

OTHER FEATURES

•

Multiple microprocessor interface modes: EPROM, Multiplexed,

Intel, Motorola and Serial

IEEE 1149.1 JTAG Boundary Scan

Single 3.3 V operation with 5 V tolerant CMOS I/Os

100-pin TQFP package, Green package options available

•

Supports programmable DPLL bandwidth (0.5 mHz to 560 Hz in 19

steps) and damping factor (1.2 to 20 in 5 steps)

APPLICATIONS

-5

-8

•

Supports 1.1X10 ppm absolute holdover accuracy and 4.4X10

•

BITS / SSU

SMC / SEC (SONET / SDH)

ppm instantaneous holdover accuracy

Supports PBO to minimize phase transients on T0 DPLL output to

be no more than 0.61 ns

Supports phase absorption when phase-time changes on T0

selected input clock are greater than a programmable limit over an

interval of less than 0.1 seconds

Supports programmable input-to-output phase offset adjustment

Limits the phase and frequency offset of the outputs

Supports manual and automatic selected input clock switch

DWDM cross-connect and transmission equipments

Central Office Timing Source and Distribution

Core and access IP switches / routers

Gigabit and Terabit IP switches / routers

IP and ATM core switches and access equipments

Cellular and WLL base-station node clocks

Broadband and multi-service access equipments

Any other telecom equipments that need synchronous equipment

system timing

•

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

March 02, 2009

 2008 Integrated Device Technology, Inc.

DSC-6772/4

1...6 7 8910 11 12...167

下载PDF

与82V3280DQG相关器件

型号	品牌	描述	获取价格	数据表
82V3280DQG8	IDT	Clock Generator, PQFP100	获取价格
82V3280PF8	IDT	Clock Generator, PQFP100	获取价格
82V3285DQ	IDT	Telecom Circuit, 1-Func, PQFP100, TQFP-100	获取价格
82V3285DQ8	IDT	Telecom Circuit, 1-Func, PQFP100, TQFP-100	获取价格
82V3285DQG8	IDT	Telecom Circuit, 1-Func, PQFP100, GREEN, TQFP-100	获取价格
82V3285EQG8	IDT	TQFP-100, Reel	获取价格

与82V3280DQG相关文章

STM32H743技术深度剖析与应用案例探索
2024-05-30

17
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
2024-05-30

16
74HC14芯片资料介绍：性能特性分析、引脚介绍
2024-05-30

14
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
2024-05-30

11

产品中心

服务支持

精选活动

关于我们

帮助中心

82V3280DQG

82V3280DQG 技术参数

82V3280DQG 数据手册

与82V3280DQG相关器件

与82V3280DQG相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

82V3280DQG

82V3280DQG 技术参数

82V3280DQG 数据手册

与82V3280DQG相关器件

与82V3280DQG相关文章

您还可以找

您在本页遇到什么问题？