INTEL 82443LX (PAC)
E
4.0. FUNCTIONAL DESCRIPTION...............................................................................................................76
4.1. System Address Map .........................................................................................................................76
4.1.1. MEMORY ADDRESS RANGES ..................................................................................................76
4.1.1.1. Compatibility Area.................................................................................................................76
Extended Memory Area .....................................................................................................................78
4.1.1.2. A.G.P. Memory Address Ranges ..........................................................................................79
4.1.1.3. A.G.P. Graphics Aperture......................................................................................................79
4.1.1.4. Address Mapping of PCI Devices on A.G.P. .........................................................................80
4.1.2. SYSTEM MANAGEMENT MODE (SMM) MEMORY RANGE......................................................80
4.1.3. MEMORY SHADOWING .............................................................................................................80
4.1.4. I/O ADDRESS SPACE.................................................................................................................80
4.1.5. PAC DECODE RULES AND CROSS-BRIDGE ADDRESS MAPPING ........................................81
4.1.5.1. PCI Interface Decode Rules..................................................................................................81
4.1.5.2. A.G.P. Interface Decode Rules .............................................................................................82
4.1.5.3. Legacy VGA and MDA Ranges.............................................................................................82
4.2. Host Interface.....................................................................................................................................83
4.3. DRAM Interface..................................................................................................................................84
4.3.1. DRAM ORGANIZATION AND CONFIGURATION .......................................................................85
4.3.1.1. Configuration Mechanism for DIMMs ....................................................................................91
4.3.2. DRAM ADDRESS TRANSLATION AND DECODING..................................................................92
4.3.3. REFRESH CYCLES (CAS# BEFORE RAS#)..............................................................................94
4.3.4. DRAM SUBSYSTEM POWER MANAGEMENT ..........................................................................94
4.3.5. SERIAL PRESENCE DETECT (SPD) FOR SDRAM ...................................................................94
4.3.6. SINGLE CLOCK COMMAND MODE FOR SDRAM.....................................................................95
4.3.6.1. Enabling Single Clock Command Mode ................................................................................97
4.3.6.2. Restrictions For Supporting Single Clock Command Mode ...................................................97
4.3.6.3. Conclusion For Single Clock Command Mode Support.........................................................97
4.3.7. SUPPORT FOR 2 AND 4 BANKS SDRAM..................................................................................97
4.4. Data Integrity Support.........................................................................................................................98
4.4.1. ECC GENERATION.....................................................................................................................98
4.4.1.1. Error Detection and Correction..............................................................................................99
4.4.1.2. ECC Test Diagnostic Mode of Operation.............................................................................100
4.5. PCI Interface ....................................................................................................................................101
4.6. A.G.P. Interface................................................................................................................................101
4.7. Arbitration and Concurrency .............................................................................................................103
4.8. System Clocking and Reset..............................................................................................................105
4.8.1. HOST FREQUENCY SUPPORT ...............................................................................................105
4.8.2. CLOCK GENERATION AND DISTRIBUTION............................................................................105
4.8.3. SYSTEM RESET.......................................................................................................................106
4.8.4. PAC RESET STRUCTURE........................................................................................................106
4.8.5. HARD RESET............................................................................................................................106
4.8.6. SOFT RESET ............................................................................................................................108
4.8.7. CPU BIST..................................................................................................................................108
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