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82437MX PDF预览

82437MX

更新时间: 2024-10-01 19:55:19
品牌 Logo 应用领域
英特尔 - INTEL 动态存储器外围集成电路
页数 文件大小 规格书
70页 498K
描述
DRAM Controller, CMOS, PQFP208, QFP-208

82437MX 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:FQFP,针数:208
Reach Compliance Code:compliant风险等级:5.83
地址总线宽度:12边界扫描:NO
总线兼容性:PENTIUM外部数据总线宽度:
JESD-30 代码:S-PQFP-G208长度:28 mm
低功率模式:NO端子数量:208
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装形状:SQUARE封装形式:FLATPACK, FINE PITCH
认证状态:Not Qualified座面最大高度:3.75 mm
标称供电电压:3 V表面贴装:YES
技术:CMOS端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:28 mmuPs/uCs/外围集成电路类型:MEMORY CONTROLLER, DRAM
Base Number Matches:1

82437MX 数据手册

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PRELIMINARY  
E
INTEL 430MX PCISET  
82437MX MOBILE SYSTEM CONTROLLER (MTSC)  
AND 82438MX MOBILE DATA PATH (MTDP)  
Supports the Pentium® Processor at  
iCOMP® Index 815\100 MHz, iCOMP  
Index 735/90 MHz, iCOMP Index  
1000/120, and the 75 MHz Pentium  
Processor  
¾ Standard Page Mode DRAMs  
¾ 4 RAS Lines  
¾ 4-Qword Deep Buffer for 3-1-1-1  
Posted Write Cycles  
¾ Symmetrical and Asymmetrical  
DRAMs  
¾ 3V or 5V DRAMs  
Integrated Second Level Cache  
Controller  
¾ Direct Mapped Organization  
¾ Write-Back Cache Policy  
¾ Cacheless, 256 Kbytes, and  
512 Kbytes  
¾ Standard, Burst and Pipelined Burst  
SRAMs  
¾ Cache Hit Read/Write Cycle Timings  
at 3-1-1-1 with Burst or Pipelined  
Burst SRAMs  
Fully Synchronous 25/30/33 MHz PCI  
Bus Interface  
¾ 100 MB/s Instant Access Enables  
Native Signal Processing on Pentium  
Processors  
¾ Synchronized CPU-to-PCI Interface  
for High Performance Graphics  
¾ PCI Bus Arbiter: MPIIX and Three PCI  
Bus Masters Supported  
¾ Back-to-Back Read Cycles at  
3-1-1-1-1-1-1-1 with Burst or  
Pipelined Burst SRAMs  
¾ Integrated Tag/Valid Status Bits for  
Cost Savings and Performance  
¾ Supports 3.3V SRAMs for Tag  
Address  
¾ CPU-to-PCI Memory Write Posting  
with 4-Dword Deep Buffers  
¾ Converts Back-to-Back Sequential  
CPU to PCI Memory Writes to PCI  
Burst Writes  
¾ PCI-to-DRAM Posting of 12 Dwords  
¾ PCI-to-DRAM up to 120 MB/s  
Bandwidth Utilizing Snoop Ahead  
Feature  
Integrated DRAM Controller  
¾ 64-Bit Data Path to Memory  
¾ 4 Mbytes to 128 Mbytes Main  
Memory  
¾ EDO/Hyper Page Mode DRAM  
(x-2-2-2 Reads) Provides Superior  
Cacheless Designs  
NAND Tree for Board-Level ATE Testing  
208-Pin QFP for the 82437MX System  
Controller (MTSC); 100-Pin TQFP for  
Each 82438MX Data Path (MTDP)  
The Intel 430MX PCIset consists of the 82437MX System Controller (MTSC), two 82438MX Data Paths  
(MTDP), and the 82371MX PCI I/O IDE Xcelerator (MPIIX). The PCIset forms a Host-to-PCI bridge and provides  
the second level cache control and a full function 64-bit data path to main memory. The MTSC integrates the  
cache and main memory DRAM control functions and provides bus control for transfers between the CPU,  
cache, main memory, and the PCI Bus. The second level (L2) cache controller supports a write-back cache  
policy for cache sizes of 256 Kbytes and 512 Kbytes. Cacheless designs are also supported. The cache  
memory can be implemented with either standard, burst, or pipelined burst SRAMs. An external Tag RAM is  
used for the address tag and an internal Tag RAM for the cache line status bits. For the MTSC DRAM controller,  
four rows are supported for up to 128 Mbytes of main memory. The MTSC optimized PCI interface allows the  
CPU to sustain the highest possible bandwidth to the graphics frame buffer at all frequencies. Using the snoop  
ahead feature, the MTSC allows PCI masters to achieve full PCI bandwidth. The MTDPs provide the data paths  
between the CPU/cache, main memory, and PCI. For increased system performance, the MTDPs contain read  
prefetch and posted write buffers.  
*Other brands and names are the property of their respective owners.  
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright,  
for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to those  
specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.  
COPYRIGHT © INTEL CORPORATION, 1996  
April 1996  
Order Number:290524-001  

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