PRELIMINARY
E
INTEL 440FX PCISET
82441FX PCI AND MEMORY CONTROLLER
(PMC) AND 82442FX DATA BUS
ACCELERATOR (DBX)
Supports the Pentium® Pro Processors
PCI Bus Interface
at Bus Frequencies Up To 66 Mhz
¾ Supports 32-Bit Addressing
¾ Optimized in-Order and Request
Queue
¾ Full Symmetric Multi-Processor
(SMP) Protocol for up to Two
Processors
¾ PCI Rev. 2.1, 5V Interface Compliant
¾ Greater than 100 MBps Data
Streaming for PCI to DRAM
Accesses Enables Native Signal
Processing (NSP) on Systems
Designed With the Pentium Pro
Processor
¾ Dynamic Deferred Transaction
Support
¾ GTL+ Compliant Host Bus
¾ Supports USWC Cycles
¾ Integrated Arbiter With Multi-
Transaction PCI Arbitration
Accelerator Hooks
¾ 5 PCI Bus Masters are Supported in
Addition to the Host and PCI-to-ISA
I/O Bridge
¾ Delayed Transaction Support
¾ PCI Parity Checking and Generation
Support
¾ Supports Concurrent Pentium Pro
and PCI Transactions to Main
Memory
Integrated DRAM Controller
¾ 8 MB to 1 GB Main Memory
¾ 64/72-Bit Non-Interleaved Path to
Memory
¾ FPM (Fast Page Mode), EDO
(Extended Data Out -Page Mode),
BEDO (Extended Data Out -Burst
Mode) DRAMs Providing x-222 to
x-4-4-4 Burst Capability
¾ Support for Auto Detection of
Memory Type: BEDO, EDO or FPM
¾ 8 RAS Lines Available
¾ Support for 4-, 16- and 64-Mb DRAM
Devices
Data Buffering For Increased
Performance
¾ Extensive CPU-to-DRAM and PCI-
to-DRAM Write Data Buffering
¾ Write Combining Support for CPU-
to-PCI Burst Writes
¾ Support for Symmetrical and
Asymmetrical DRAM Addressing
¾ Configurable Support for ECC or
Parity
¾ ECC with Single Bit Error
Correction and Multiple Bit Error
Detection
System Management Mode (SMM)
Compliant
208-Pin PQFP PCI Bridge/ Memory
Controller (PMC), 208-Pin PQFP for the
440FX PCIset Data Bus Accelerator
(DBX)
¾ Read-Around-Write Support for
Host and PCI DRAM Read Accesses
¾ Supports 3.3V or 5V DRAMs
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The Intel 440FX PCIset provides a highly integrated solution for systems based on one or two Pentium Pro
processors. The 440FX PCIset consists of the 82441FX PCI and Memory Controller (PMC), the 82442FX Data
Bus Accelerator (DBX), and the 82371SB PCI I/O IDE Xcelerator (PIIX3). The PMC and DBX provide a two-chip
host-to-PCI bridge including the DRAM control function, the PCI interface, and the PCI arbiter function. The
440FX PCIset supports EDO, FPM, and BEDO DRAM technologies. The DRAM controller provides support for
up to eight rows of memory and optional DRAM error detection/correction or parity. The 440FX PCIset contains
extensive buffering between all interfaces for high system data throughput and concurrent operations.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights
is granted by this document or by the sale of Intel products. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a
particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The Intel 440FX
PCIset may contain design defects or errors known as errata. Current characterized errata are available on request. Third-party brands and names are the property
of their respective owners.
© INTEL CORPORATION 1996
May 1996
Order Number: 290549-001