Datasheet > 80C52-40R

80C52-40R

更新时间： 2022-12-11 19:08:47

品牌	Logo	应用领域
TEMIC		微控制器
页数	文件大小	规格书
20页	227K
描述
CMOS 0 to 44 MHz Single-chip 8 Bit Microcontroller

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获取价格

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80C52-40R 数据手册

80C32/80C52

MATRA MHS

Note 1 : ICC is measured with all output pins

disconnected ; XTAL1 driven with TCLCH, TCHCL =

5 ns, VIL = VSS + .5 V, VIH = VCC –.5 V ; XTAL2

N.C. ; EA = RST = Port 0 = VCC. ICC would be slighty

higher if a crystal oscillator used.

Figure 9. ICC Test Condition, Idle Mode.

All other pins are disconnected.

Idle ICC is measured with all output pins disconnected ;

XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL =

VSS + 5 V, VIH = VCC –.5 V ; XTAL2 N.C ; Port 0 =

VCC ; EA = RST = VSS.

Power Down ICC is measured with all output pins

disconnected ; EA = PORT 0 = VCC ; XTAL2 N.C. ;

RST = VSS.

Note 2 : Capacitance loading on Ports 0 and 2 may cause

spurious noise pulses to be superimposed on the VOLS of

ALE and Ports 1 and 3. The noise is due to external bus

capacitance discharging into the Port 0 and Port 2 pins

when these pins make 1 to 0 transitions during bus

operations. In the worst cases (capacitive loading 100

pF), the noise pulse on the ALE line may exceed 0.45 V

may exceed 0,45 V with maxi VOL peak 0.6 V. A Schmitt

Trigger use is not necessary.

Figure 10. ICC Test Condition, Active Mode.

All other pins are disconnected.

Figure 11. ICC Test Condition, Power Down Mode.

All other pins are disconnected.

Figure 12. Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.

Rev. E (31/08/95)

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