Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC DIP
PLCC LQFP TSSOP TYPE NAME AND FUNCTION
V
20
40
22
44
16
38
9
I
I
Ground: 0 V reference.
SS
CC
V
29
Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
P0.0-0.7
39–32 43–36 37–30 28–21
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high-impedance inputs. Port 0 is also the
multiplexed low-order address and data bus during accesses to external program
and data memory. In this application, it uses strong internal pull-ups when emitting
1s. Port 0 also outputs the code bytes during program verification and received
code bytes during EPROM programming. External pull-ups are required during
program verification.
P1.0–P1.7
1–8
2–9
40–44, 30–37
1–3
I/O
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 1 pins that are externally pulled low will source current
because of the internal pull-ups. (See DC Electrical Characteristics: I ). Port 1 also
IL
receives the low-order address byte during program memory verification. Alternate
functions for Port 1 include:
1
2
2
3
40
41
30
31
T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable
Clock-Out)
I
T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control
P2.0–P2.7
21–28 24–31 18–25 10–17
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 2 pins that are externally being pulled low will source current
because of the internal pull-ups. (See DC Electrical Characteristics: I ). Port 2
IL
emits the high-order address byte during fetches from external program memory
and during accesses to external data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s.
During accesses to external data memory that use 8-bit addresses (MOV @Ri), port
2 emits the contents of the P2 special function register. Some Port 2 pins receive
the high order address bits during EPROM programming and verification.
P3.0–P3.7
10–17
11,
5,
1–6
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 3 pins that are externally being pulled low will source current
13–19 7–13
because of the pull-ups. (See DC Electrical Characteristics: I ). Port 3 also serves
IL
the special features of the 80C51 family, as listed below:
10
11
12
13
14
15
16
17
9
11
13
14
15
16
17
18
19
10
5
7
1
2
I
O
I
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
1
8
INT0 (P3.2): External interrupt
9
3
4
I
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
10
11
12
13
4
I
1
I
T1 (P3.5): Timer 1 external input
5
6
O
O
I
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
RST
38
Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to V permits a power-on reset
SS
using only an external capacitor to V
.
CC
ALE/PROG
30
33
27
19
O
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of
the address during an access to external memory. In normal operation, ALE is
emitted at a constant rate of 1/6 (12-clock Mode) or 1/3 (6-clock Mode) the
oscillator frequency, and can be used for external timing or clocking. Note that one
ALE pulse is skipped during each access to external data memory. This pin is also
the program pulse input (PROG) during EPROM programming. ALE can be
disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during
a MOVX instruction.
10
2003 Jan 24
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