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80C51BHP

更新时间: 2024-02-18 13:36:24
品牌 Logo 应用领域
英特尔 - INTEL 微控制器
页数 文件大小 规格书
21页 285K
描述
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

80C51BHP 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.57技术:CMOS
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

80C51BHP 数据手册

 浏览型号80C51BHP的Datasheet PDF文件第3页浏览型号80C51BHP的Datasheet PDF文件第4页浏览型号80C51BHP的Datasheet PDF文件第5页浏览型号80C51BHP的Datasheet PDF文件第7页浏览型号80C51BHP的Datasheet PDF文件第8页浏览型号80C51BHP的Datasheet PDF文件第9页 
87C51/80C51BH/80C31BH  
IDLE MODE  
the on-chip RAM. An external interrupt allows both  
the SFRs and on-chip RAM to retain their values.  
In Idle Mode, the CPU puts itself to sleep while all  
the on-chip peripherals remain active. The mode is  
invoked by software. The content of the on-chip  
RAM and all the Special Functions Registers remain  
unchanged during this mode. The Idle Mode can be  
terminated by any enabled interrupt or by a hard-  
ware reset.  
To properly terminate Power Down, the reset or ex-  
ternal interrupt should not be executed before V is  
restored to its normal operating level, and must be  
held active long enough for the oscillator to restart  
and stabilize (normally less than 10 ms).  
CC  
With an external interrupt INT0 and INT1 must be  
enabled and configured as level-sensitive. Holding  
the pin low restarts the oscillator but bringing the pin  
back high completes the exit. Once the interrupt is  
serviced, the next instruction to be executed after  
RET1 will be the one following the instruction that  
put the device into Power Down.  
It should be noted that when Idle is terminated by a  
hardware reset, the device normally resumes pro-  
gram execution, from where it left off, up to two ma-  
chine cycles before the internal reset algorithm  
takes control. On-chip hardware inhibits access to  
internal RAM in this event, but access to the port  
pins is not inhibited. To eliminate the possibility of an  
unexpected write to a port pin when Idle is terminat-  
ed by reset, the instruction following the one that  
invokes Idle should not be one that writes to a port  
pin or to external memory.  
DESIGN CONSIDERATIONS  
Exposure to light when the device is in operation  
#
may cause logic errors. For this reason, it is sug-  
gested that an opaque label be placed over the  
window when the die is exposed to ambient light.  
POWER DOWN MODE  
The 87C51/BH now have some additional fea-  
#
To save even more power, a Power Down mode can  
be invoked by software. In this mode, the oscillator  
is stopped and the instruction that invoked Power  
Down is the last instruction executed. The on-chip  
RAM and Special Function Registers retain their val-  
ues until the Power Down mode is transmitted.  
tures. The features are: asynchronous port reset,  
4 interrupt priority levels, power off flag, ALE dis-  
able, serial port automatic address recognition,  
serial port framing error detection, 64-byte en-  
cryption array, and 3 program lock bits. These  
features cannot be used with the older versions  
of 80C51BH/80C31BH. The newer version of  
80C51BH/80C31BH will have change identifier  
‘‘A’’ appended to the lot number.  
On the 87C51/BH either a hardware reset or an ex-  
ternal interrupt can cause an exit from Power Down.  
Reset redefines all the SFR’s but does not change  
Table 2. Status of the External Pins during Idle and Power Down  
Program  
Memory  
Mode  
Idle  
ALE  
PSEN  
PORT0  
PORT1  
PORT2  
PORT3  
Internal  
External  
Internal  
External  
1
1
0
0
1
1
0
0
Data  
Float  
Data  
Float  
Data  
Data  
Data  
Data  
Data  
Address  
Data  
Data  
Data  
Data  
Data  
Idle  
Power Down  
Power Down  
Data  
6

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