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80523TX266512 PDF预览

80523TX266512

更新时间: 2024-01-04 23:09:56
品牌 Logo 应用领域
英特尔 - INTEL 信息通信管理外围集成电路
页数 文件大小 规格书
67页 718K
描述
RISC Microprocessor, 32-Bit, 266MHz, BICMOS, MBGA240

80523TX266512 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:compliantECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.77
地址总线宽度:36位大小:32
边界扫描:YES最大时钟频率:66.67 MHz
外部数据总线宽度:64格式:FIXED POINT
集成缓存:YESJESD-30 代码:R-XXMA-X
低功率模式:YES封装主体材料:UNSPECIFIED
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
认证状态:Not Qualified速度:266 MHz
最大供电电压:1.72 V最小供电电压:1.48 V
标称供电电压:1.6 V表面贴装:NO
技术:CMOS端子形式:UNSPECIFIED
端子位置:UNSPECIFIEDuPs/uCs/外围集成电路类型:MICROPROCESSOR
Base Number Matches:1

80523TX266512 数据手册

 浏览型号80523TX266512的Datasheet PDF文件第1页浏览型号80523TX266512的Datasheet PDF文件第2页浏览型号80523TX266512的Datasheet PDF文件第3页浏览型号80523TX266512的Datasheet PDF文件第5页浏览型号80523TX266512的Datasheet PDF文件第6页浏览型号80523TX266512的Datasheet PDF文件第7页 
®
MOBILE PENTIUM PROCESSOR WITH MMX™ TECHNOLOGY  
2.0. MICROPROCESSOR  
ARCHITECTURE OVERVIEW  
1.0. INTRODUCTION  
The mobile Pentium processor with MMX  
technology on 0.25 micron extends the mobile  
Pentium processor with MMX technology family. It  
is binary compatible with the 8086/88™, 80286™,  
Intel386™ DX, Intel386 SX, Intel486™ DX,  
Intel486 SX, Intel486 DX2, and mobile Pentium  
processors with voltage reduction technology (75-  
150).  
The mobile Pentium® processors with MMX™  
technology on 0.25 micron are fully compatible  
with the existing mobile Pentium processors with  
MMX technology (120, 133, 150, & 166 MHz) with  
the following differences: voltage supplies, power  
consumption,  
and  
performance.  
These  
processors, when used in a TCP package, are  
socket compatible with the mobile Pentium  
processor (75, 90, 100, 120, 133, 150 MHz)  
making it possible to design a flexible motherboard  
that supports both the mobile Pentium processor  
(75 MHz - 150 MHz) and the mobile Pentium  
processor with MMX technology (120 MHz - 266  
MHz). It has all the advanced features of the  
desktop version of the Pentium processor with  
MMX technology except for the differences listed  
in Section 3.1.  
The mobile Pentium processor family consists of  
the mobile Pentium processor with MMX  
technology (120, 133, 150, & 166), The mobile  
Pentium processor with MMX technology on 0.25  
micron (166, 200, 233, & 266) and the mobile  
Pentium processor with voltage reduction  
technology (75 MHz -150 MHz).  
The mobile Pentium processor with MMX  
technology on 0.25 micron contains all of the  
features of previous Intel Architecture and  
provides significant enhancements and additions  
including the following:  
The mobile Pentium processor with MMX  
technology on 0.25 micron has several features  
which allow high-performance notebooks to be  
designed, including the following:  
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Support for MMX™ Technology  
Superscalar Architecture  
·
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TCP dimensions are ideal for small form-factor  
designs.  
Enhanced Branch Prediction Algorithm  
Pipelined Floating-Point Unit  
Improved Instruction Execution Time  
Separate 16K Code and 16K Data Caches  
Writeback MESI Protocol in the Data Cache  
64-Bit Data Bus  
TCP has superior thermal resistance  
characteristics.  
1.8V (166/200/233 MHz)/2.0V (266 MHz) core  
and 2.5V I/O buffer VCC inputs reduce power  
consumption significantly.  
·
The SL Enhanced feature set.  
Enhanced Bus Cycle Pipelining  
Address Parity  
The architecture and internal features of the  
mobile Pentium processor with MMX technology  
on 0.25 micron are identical to the desktop version  
specifications provided in the Pentium® Processor  
Family Developers Manual (Order Number  
241428), except several features not used in  
mobile applications which have been eliminated to  
streamline it for mobile applications.  
Internal Parity Checking  
Execution Tracing  
Performance Monitoring  
IEEE 1149.1 Boundary Scan  
System Management Mode  
Virtual Mode Extensions  
This document should be used in conjunction with  
Pentium® Processor Family Developers Manual  
(Order Number: 241428)  
0.25 Micron Process Technology  
SL Power Management Features  
Pool of four write buffers used by both pipes  
4

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