Data Sheet
SC-605
DC Electrical Characteristics, TA = 0 to 70°C
PARAMETER
TEST CONDITIONS
MIN TYP§ MAX UNIT
Positive going threshold
Negative going threshold
Hysteresis
2.4
VDD = 3 V
V
V
V
V
1.8
0.6
3.3
2.9
0.4
RESET_ Threshold changes
Positive going threshold
Negative going threshold
Hysteresis
V
DD = 5.2 V
VDD = 3 V
2
3
3
4.5
5.2
1
1.5
1.7
–2
5
VIH
VIL
High-level input voltage
Low-level input voltage
VDD = 4.5 V
VDD = 5.2 V
VDD = 3 V
3.5
0
VDD = 4.5 V
VDD = 5.2 V
0
0
¶
IOH
High-level output current per pin of I/O port
Low-level output current per pin of I/O port
High-level output DAC current
Low-level output DAC current
Input leakage current
VOH = 4 V
VOL = 0.5 V
VOH = 4 V
VOL = 0.5 V
mA
mA
mA
mA
µA
µA
mA
¶
IOL
V
DD = 4.5 V
IOH (DAC)
IOL (DAC)
Ilkg
–10
20
1
Excludes OSCIN
RESET is low
I(STANDBY) Standby current
0.05
15
10
†
IDD
Operating current
VDD = 4.5 V, FCLOCK = 12.32 MHz
VDD = 4.5 V, DAC off, ARM set, OSC disabled
VDD = 4.5 V, DAC off, ARM set, OSC enabled
VDD = 4.5 V, DAC off, ARM clear, OSC enabled
VDD = 4.5 V, Vref = 1 to 4.25 V
I(SLEEP-deep)
I(SLEEP-mid)
I(SLEEP-light)
VIO
0.05
40
10
60
100
50
Supply current
µA
60
25
Input offset voltage
mV
KΩ
R(PULLUP) F port pullup resistance
VDD = 5 V
70 150
R
RTO = 470 kΩ, VDD = 4.5 V, TA = 25°C,
RTO = 8.192 MHz (PLL setting = 7 Ch)‡
RTO = 470 kΩ, VDD = 3.5 to 5.2 V, TA = 25°C,
RTO = 8.192 MHz (PLL setting = 7 Ch)‡
RTO = 470 kΩ, VDD = 4.5 V, TA = 0 to 70°C,
fRTO = 8.192 MHz (PLL setting = 7 Ch)‡
DD = 4.5 V, TA = 25°C, R(OSC) = 470 kΩ at ±1%,
RTO = 8.192 MHz (PLL setting = 7 Ch)‡
∆f(RTO-trim) Trim deviation
±1% ±3%
f
R
∆f(RTO-volt) Voltage deviation
±1.5%
f
R
∆f(RTO-temp) Temperature deviation
∆f(RTO-res) Resistance deviation
±0.03
%/°C
V
±1%
f
† Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC
output and other outputs are open circuited.
‡ The best trim value is selected at nominal temperature and voltage but the deviation due to the trim error is ignored.
§ Typical voltage and current measurement taken at 25°C
¶ Cannot exceed 15 mA total per internal VDD pin. Port A, B share 1 internal VDD pin; Port C, D share 1 internal VDD
.
External Component Absolute Values
PARAMETER
R(RTO)
TEST CONDITIONS
MIN
MAX
470
3300
UNIT
k
pF
RTO external resistance
PLL external capacitance
TA = 25°C, 1% tolerance
TA = 25°C, 10% tolerance
C(PLL)
© 2002 Sensory Inc.
P/N 80-0209-A
5