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80-0209-A

更新时间： 2022-12-16 17:50:07

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80-0209-A 数据手册

SC-605

Data sheet

The data memory is internal static RAM. The RAM is configured in 640 17-bit words. All memories are designed

to consume minimum power at a given system clock and algorithm acquisition frequency.

A flexible clock generation system enables the software to control the clock over a wide frequency range. The

implementation uses a phase-locked loop (PLL) circuit that drives the processor clock at a selectable frequency

between the minimum and maximum achievable. Selectable frequencies for the processor clock are spaced

apart in 65.536 kHz steps. The PLL clock-reference is also selectable; either a resistor-trimmed oscillator or a

crystal-referenced oscillator may be used. Internal and external clock sources are controlled separately to

provide different levels of power management.

The periphery consists of five 8-bit wide general-purpose I/O ports, one 8-bit wide dedicated input port, and one

16-bit wide dedicated output port. The bidirectional I/O can be configured under software control as either high-

impedance inputs or as totem-pole outputs. They are controlled via addressable I/O registers. The input-only

port has a programmable pullup option (70k minimum resistance) and a dedicated service interrupt. These

features make the input port especially useful as a key-scan interface.

A simple one-bit comparator is also included in the periphery. The comparator is enabled by a control register,

and its pin access is shared with two pins in one of the general-purpose I/O ports. Rounding out the SC-605

periphery is a built-in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive

capability. The functional block diagram gives an overview of the SC-605 functionality.

Functional Block Diagram

P/N 80-0209-A

123 4 5 6 7 8

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