Datasheet > 7C132-25

7C132-25

更新时间： 2022-11-26 04:28:33

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
18页	341K
描述
2Kx8 Dual-Port Static RAM

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数据手册

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7C132-25 数据手册

CY7C132/CY7C136

CY7C142/CY7C146

Switching Waveforms (continued)

[15, 23]

Write Cycle No.1 (OE Three-States Data I/Os-Either Port)

ADDRESS

SCE

PWE

R/W

DATA

DATA VALID

HZOE

HIGH IMPEDANCE

OUT

C132-10

[15, 24]

Write Cycle No. 2 (R/W Three–States Data I/Os-Either Port)

ADDRESS

SCE

PWE

R/W

DATA

DATA VALID

LZWE

HZWE

HIGH IMPEDANCE

OUT

C132-11

Notes:

23. If OEis LOW during a R/W controlled write cycle, the write pulse width must be the larger of t_PWEor t_HZWE+ t_SDto allow the data I/O pins to enter high impedance and for data

to be placed on the bus for the required t_SD

24. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state.

1...5 6 789 10 11...18

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