7B991

更新时间： 2024-02-17 15:22:00

品牌	Logo	应用领域
麦斯威 - MAXWELL		时钟
页数	文件大小	规格书
17页	246K
描述
Programmable Skew Clock Buffer (PSCB)

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7B991 技术参数

生命周期：	Active	包装说明：	RAD PAK, DFP-16
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.6	输入调节：	STANDARD
JESD-30 代码：	R-XDFP-F32	长度：	20.828 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	32
实输出次数：	8	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	DFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	1.2 ns	座面最大高度：	3.7338 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子形式：	FLAT
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	12.192 mm	最小 fmax：	80 MHz
Base Number Matches：	1

7B991 数据手册

7B991

Programmable Skew Clock Buffer (PSCB)

1,2,3

TABLE 7. AC ELECTRICAL CHARACTERISTICS

(V_CC= 5V ±10%, T_A= -40 TO 85°C, UNLESS OTHERWISE SPECIFIED)

P^ARAMETER

SYMBOL

SUBGROUPS

MIN

TYP

MAX

UNIT

Output HIGH Time Deviation from 50% ^14,15

Output LOW Time Deviation from 50% ^14,15

Output Rise Time ^14,16

t_PWH

t_PWL

9, 10, 11

3.5

2.5

0.5

200

t_ORISE

t_OFALL

t_LOCK

t_JR

0.15

1.5

Output Fall Time ^14,16

PLL Lock Time ¹⁷

Cycle-to-Cycle Output Jitter

Peak-to-

Peak ³

1. The level to be set of FS in determined by the “normal” operating frequency (f_NOM) of the V_COand Time Unit Generator (see

Logic Block Diagram). Nominal frequency (f_NOM) always appears at 1Q0 and the other outputs when they are operated in their

undivided modes (See Table 9). The frequency appearing at the REF and FB inputs will be f_NOMwhen the output connected to

FB is undivided. The frequency of the REF and FB inputs will be f_NOM/2 or f_NOM/4 when the part is configured for a frequency

multiplication by using a divided output as the FB input.

2. Test measurement levels for the 7B991 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or

less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.

3. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.

4. For all three state inputs. HIGH indicates a connection to V , LOW indicates a connection to GND, and MID indicates an open

connections. Internal termination circuitry holds an unconnected input to V /2.

5. When the FS pin is selected HIGH, the REF input must not transition upon power-up until V_CChas reached 4.3V.

6. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t_Udelay

has been selected when all are loaded with 50 pF and terminated with 50Ω to 2.06V.

7. t_SKEWPRis defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0t_U.

8. t_SKEW0is defined as the skew between outputs when they are selected for 0t_U. Other outputs are divided or inverted but not

shifted.

9. C_L= 0 pF. For C_L= 30 pF, t_SKEW0= 0.35 ns.

10.There are three classes of outputs: Nominal (multiple of t_Udelay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and

divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).

11. t_DEVis the output-to-output skew between any two devices operating under the same conditions (V_CCambient temperature, air

flow, etc.)

12.Guaranteed by design.

13.t_ODCVis the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t_SKEW2and t_SKEW4spec-

ifications.

14.Specified with outputs loaded 30 pF for the 7B99 devices. Devices are terminated through 50Ω to 2.05V.

15.t_PWHis measured at 2.0V. t_PWLis measured at 0.8V.

16.t_ORISEand t_OFALLmeasured between 0.8V and 2.0V.

17.t_LOCKis the time that is required before synchronization is achieved. This specification is valid only after V_CCis stable and within

normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t_PDis

within specified limits.

09.23.02 Rev 4

All data sheets are subject to change without notice

1...3 4 567 8 9...17

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