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7B991

更新时间: 2024-01-11 10:13:25
品牌 Logo 应用领域
麦斯威 - MAXWELL 时钟
页数 文件大小 规格书
17页 246K
描述
Programmable Skew Clock Buffer (PSCB)

7B991 技术参数

生命周期:Active包装说明:RAD PAK, DFP-16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.6输入调节:STANDARD
JESD-30 代码:R-XDFP-F32长度:20.828 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:32
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:DFP封装形状:RECTANGULAR
封装形式:FLATPACK认证状态:Not Qualified
Same Edge Skew-Max(tskwd):1.2 ns座面最大高度:3.7338 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
宽度:12.192 mm最小 fmax:80 MHz
Base Number Matches:1

7B991 数据手册

 浏览型号7B991的Datasheet PDF文件第1页浏览型号7B991的Datasheet PDF文件第2页浏览型号7B991的Datasheet PDF文件第3页浏览型号7B991的Datasheet PDF文件第5页浏览型号7B991的Datasheet PDF文件第6页浏览型号7B991的Datasheet PDF文件第7页 
7B991  
Programmable Skew Clock Buffer (PSCB)  
TABLE 5. 7B991 DC ELECTRICAL CHARACTERISTICS  
(VCC = 5V ±10%, TA = -40 TO 85°C, UNLESS OTHERWISE SPECIFIED)  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
SUBGROUPS  
MIN  
MAX  
UNIT  
Input HIGH Current (Test, FS, xFn)  
Input MID Current (Test, FS, xFn)  
Input LOW Current (Test, FS, xFn)  
I
V = V  
CC  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1
--  
-200  
--  
200  
200  
µA  
µA  
µA  
mA  
IH  
IN  
I
V = 2.75  
IMM  
IN  
I
V = GND  
-200  
-250  
ILL  
IN  
Output Short Circuit (Test, FS, xFn)  
2
IOS  
V
CC = Max., VOUT = GND  
(25 °C only)  
CCN = VCCQ = Max, all input  
selects open  
--  
Operating Current used by Internal  
Circuitry  
ICCQ  
ICCN  
V
1, 2, 3  
1, 2, 3  
--  
--  
90  
14  
mA  
mA  
Output Buffer Current per Output  
Pair 3  
V
CCN = VCCQ = Max,  
OUT = 0 mA,  
Input selects open, fMAX  
CCN = VCCQ = Max,  
OUT = 0 mA  
Input selects open, fMAX  
I
Power Dissipation per Output Pair 4  
PD  
V
I
1, 2, 3  
--  
78  
mW  
1. These inputs are normally wired to V ,GND, or left unconnected (actual threshold voltages vary as a percentage of V ). Inter-  
CC  
CC  
nal termination resistors hold unconnected inputs at V /2. If these inputs are switched, the function and timing of the outputs  
CC  
may glitch and the PLL may require an additional tLOCK time before all datasheet limits are achieved.  
2. This device should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room  
temperature only.  
3. Total output current per output pair can be approximated by the following expression that includes device current plus load cur-  
rent:  
ICCN = [(4 + 0.11F) + [((835-3F)/Z) + (.0022FC)]N] x 1.1  
Where:  
f = frequency in MHz  
C = capacitive load in pF  
Z = line impedance in ohms  
N = number of loaded outputs; 0, 1, or 2  
FC = F * C  
4. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation  
due to the load circuit:  
PD = [(22 + 0.61F) + [((1550-2.7F)/Z) + (.0125FC)]N] x 1.1  
1
TABLE 6. 7B991 CAPACITANCE  
PARAMETER  
Input Capacitance  
1. Guaranteed by design.  
SYMBOL  
TEST CONDITIONS  
MAX  
UNIT  
CIN  
T = 25 °C, f = 1 MHz, VCC = 5.0V  
10  
pF  
A
09.23.02 Rev 4  
All data sheets are subject to change without notice  
4
©2002 Maxwell Technologies.  
All rights reserved.  

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