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78P2351-IGTR/F PDF预览

78P2351-IGTR/F

更新时间： 2024-02-01 14:49:03
品牌 Logo 应用领域
美信 - MAXIM ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
42页 736K
描述
Transceiver, 1-Func, CMOS, PQFP100, LEAD FREE, LQFP-100

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78P2351-IGTR/F 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Not Recommended零件包装代码：QFP
包装说明：LFQFP, QFP100,.63SQ,20针数：100
Reach Compliance Code：compliantECCN代码：5A991
HTS代码：8542.39.00.01Factory Lead Time：7 weeks
风险等级：5.41应用程序：SDH
JESD-30 代码：S-PQFP-G100长度：14 mm
湿度敏感等级：3功能数量：1
端子数量：100最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP100,.63SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Digital Transmission Interfaces最大压摆率：0.212 mA
标称供电电压：3.3 V表面贴装：YES
技术：CMOS电信集成电路类型：ATM/SONET/SDH TRANSCEIVER
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

78P2351-IGTR/F 数据手册

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78P2351  
Single Channel  
OC-3/ STM1-E/ E4 LIU  
LOOPBACK MODES  
In SW mode, LLBK and RLBK bits in the Signal  
Control register are provided to activate the local  
and remote analog loopback modes respectively.  
In HW mode, the LPBK pin can be used to activate  
local and remote analog loopback paths as shown in  
the table below.  
In SW mode only, a Full Remote (digital) Loopback  
bit FLBK is also available in the Advanced Tx  
Control register. This loopback exercises the entire  
Rx and Tx paths of the 78P2351 including the Tx  
clock recovery unit. As such, the user must enable  
either Serial Plesiochronous or Serial Loop-timing  
transmit modes to utilize the Full Remote (digital)  
Loopback.  
EACH CHANNEL: Tx  
Lock Detect  
LPBK pin Loopback Mode  
ECLxP/N  
Tx CDR  
TXxCKP/N  
SIxDP/N  
FIFO  
CMI  
Encoder  
Low  
Normal operation  
Remote (analog) Loopback:  
SIxCKP/N  
CMIxP/N  
PIxCK  
PIx[3:0]D  
PTOxCK  
PMOD, SMOD[1:0], PAR  
Recovered receive clock and data  
looped back directly to the transmit  
driver. The CMI decoder and most of  
transmit path is bypassed (including the  
redundant Tx monitor output)  
RLBK  
Float  
SOxCKP/N  
SOxDP/N  
CMI  
Decoder  
Rx CDR  
Adaptive  
Eq.  
RXxP/N  
POx[3:0]D  
POxCK  
Lock Detect  
LOS Detect  
CMI  
LLBK  
EACH CHANNEL: Rx  
Local (analog) Loopback:  
Figure 9: Remote (Digital) Loopback  
High  
Transmit clock and data looped back to  
receiver at the analog media interface.  
INTERNAL POWER-ON RESET  
Lock Detect  
Power-On Reset (POR) function is provided on chip.  
Roughly 50 µs after Vcc reaches 2.4V at power up,  
a reset pulse is internally generated. This resets all  
registers to their default values as well as all state  
machines within the transceiver to known initial  
values. The reset signal is also brought out to the  
PORB pin. The PORB pin is a special function  
analog pin that allows for the following:  
ECLP/N  
TXCKP/N  
SIDP/N  
Tx CDR  
FIFO  
CMI  
Encoder  
CMI2P/N  
CMIP/N  
SICKP/N  
PICK  
PI[3:0]D  
PTOCK  
PMOD, SMOD[1:0], PAR  
RLBK,  
RDSL  
SOCKP/N  
SODP/N  
CMI  
Rx CDR  
Decoder  
Adaptive  
Eq.  
RXP/N  
PO[3:0]D  
POCK  
Lock Detect  
LOS Detect  
CMI  
LLBK  
•
•
•
Override the internal POR signal by driving in  
Figure 7: Local (Analog) Loopback  
an external active low reset signal;  
Use the internally generated POR signal to  
trigger other resets;  
Add external capacitor to slow down the  
release of power-on reset (approximately 8µs  
per nF added).  
Lock Detect  
Tx CDR  
ECLP/N  
TXCKP/N  
SIDP/N  
FIFO  
CMI  
Encoder  
CMI2P/N  
CMIP/N  
SICKP/N  
PICK  
NOTE: Do not pull-up the PORB pin to Vcc or drive  
this pin high during power-up. This will prevent the  
internal reset generator from resetting the entire chip  
and may result in errors.  
PI[3:0]D  
PTOCK  
PMOD, SMOD[1:0], PAR  
RLBK,  
RDSL  
SOCKP/N  
SODP/N  
CMI  
Rx CDR  
Decoder  
Adaptive  
Eq.  
RXP/N  
PO[3:0]D  
POCK  
Lock Detect  
LOS Detect  
CMI  
LLBK  
Figure 8: Remote (Analog) Loopback  
Page: 8 of 42  
2006 Teridian Semiconductor Corporation  
Rev. 2.4  
1...567891011...42

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