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78P2344-IEL/A07R/F PDF预览

78P2344-IEL/A07R/F

更新时间: 2024-02-23 03:31:53
品牌 Logo 应用领域
TERIDIAN /
页数 文件大小 规格书
37页 353K
描述
Telecom IC, PQFP100,

78P2344-IEL/A07R/F 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:QFP, QFP100,.63SQ,20Reach Compliance Code:compliant
风险等级:5.41运营商类型:E-3
运营商类型(2):STS-1/OC-1运营商类型(3):T-3(DS3)
JESD-30 代码:S-PQFP-G100端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK电源:3.3 V
认证状态:Not Qualified子类别:Other Telecom ICs
最大压摆率:355 mA标称供电电压:3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD

78P2344-IEL/A07R/F 数据手册

 浏览型号78P2344-IEL/A07R/F的Datasheet PDF文件第5页浏览型号78P2344-IEL/A07R/F的Datasheet PDF文件第6页浏览型号78P2344-IEL/A07R/F的Datasheet PDF文件第7页浏览型号78P2344-IEL/A07R/F的Datasheet PDF文件第9页浏览型号78P2344-IEL/A07R/F的Datasheet PDF文件第10页浏览型号78P2344-IEL/A07R/F的Datasheet PDF文件第11页 
78P2344JAT  
4-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
REGISTER DESCRIPTION (continued)  
LEGEND  
TYPE DESCRIPTION  
TYPE DESCRIPTION  
R/W Read or Write  
R/O  
Read only  
GLOBAL REGISTERS  
ADDRESS 0-0: MASTER CONTROL REGISTER  
DFLT  
BIT  
NAME  
TYPE  
DESCRIPTION  
VALUE  
Register Control Enable:  
0 : Pin selection overrides register settings  
7
REGEN  
R/W  
0
1 : Device is controlled via register set.  
NOTE: Pin 15 (ENDECB) must be tied low when REGEN is enabled.  
Line Speed Selection:  
Selects the line speed of all channels as well as the input clock frequency  
at the CKREF pin.  
6
5
DS3  
E3  
R/W  
R/W  
X
X
[DS3 E3] = 00 : STS-1 (51.840MHz)  
01 : E3 (34.368MHz)  
10 : DS3 (44.736MHz)  
11 : STS-1 (51.840MHz)  
NOTE: The default values of these register bits depend on the state of  
the MSL0 pin upon power-up or reset.  
Encoder/Decoder Disable:  
0 : selects NRZ digital data interface  
4
3
ENDECB  
RCLKP  
R/W  
R/W  
0
0
1 : selects AMI digital data interface  
NOTE: Relevant only when the REGEN bit is set. Otherwise, ENDECB  
pin selection prevails.  
RCLK Polarity Selection:  
0 : Receive Data clocked out on the falling-edge of RCLK  
1 : Receive Data clocked out on the rising-edge of RCLK  
TCLK Polarity Selection:  
2
1
TCLKP  
RSVD  
R/W  
R/O  
0
0 : Transmit Data clocked in on the rising-edge of TCLK  
1 : Transmit Data clocked in on the falling-edge of TCLK  
--  
Reserved  
Register Soft-Reset:  
When this bit is set, all registers are reset to their default values. Also  
resets Jitter Attenuator to “centered” states. This register bit is self-  
clearing.  
0
SRST  
R/W  
0
Page 8 of 37  
2005 Teridian Semiconductor Corporation  
Rev 2.2  

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