78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
RCLK/TCLK POLARITY REVERSAL
SERIAL CONTROL INTERFACE
To simplify the interface with various framer
circuitries, clock polarities can be set with the ICKP
pin as described in the table below. Alternately,
TCLK polarity can be internally inverted by setting
the TCLKP bit, and RCLK polarity can be inverted
by setting the RCLKP bit. Both bits are located in
the Master Control Register (MSCR) and are only
active when the Register Control Enable (REGEN)
bit is enabled.
The serial port controlled register allows a generic
controller to interface with the 78P2341JAT. It is
used for mode settings, diagnostics and test, and
the retrieval of status and performance information.
The serial interface consists of two pins: Serial
Clock (SCK) and Serial Data In and Out (SDIO).
Serial Data In (SDI) and Serial Data Out (SDO) are
connected together internally to simplify the
operation. SCK is the clock input that times the data
on SDIO. Data on SDI is latched in on the rising-
edge of SCK, and data on SDO is clocked out using
the falling edge of SCK.
SDI is used to insert mode, address, and register
data into the chip. Address and Data information
are input least significant bit (LSB) first. The mode
and address bit assignment and register table are
shown in the following section.
ICKP
RCLK/TCLK polarity
Update on falling edge of RCLK
Sample on rising edge of TCLK
Update on rising edge of RCLK
Sample on falling edge of TCLK
Update on falling edge of RCLK
Sample on falling edge of TCLK
L
Z
H
SDO is a tristate capable output. It is used to output
register data during a read operation. SDO output is
normally high impedance, and is enabled only
during the duration when register data is being
clocked out. Read data is clocked out significant bit
(LSB) first.
The maximum clock frequency for register access is
20MHz, while the minimum is 5MHz. There must be
at least 10us between clock bursts.
POWER-DOWN FUNCTION
Power-down controls are provided to allow the
transceiver to be shut off. Transmit and receive
power-down can be set independently via the PDTX
and PDRX bits in the Mode Control Register. The
Serial Control Interface and Configuration Registers
are not affected by power-down.
INTERNAL POWER-ON RESET
The 78P2341JAT includes on-chip Power-On Reset
(POR) function to ensure the serial-port registers are
initialized to known default states upon power-up.
This reset signal also sets all state machines within
the transceiver to nominal operational states. The
internal reset signal is also brought out to the POR
pin. This pin is a multi-function pin which allows for
the following:
1) Override the internal POR signal by driving in an
external active-low reset signal;
2) Monitor the state of the internal POR signal (for
test and debug only);
3) Add external capacitor to delay the release of
the internal power-on reset signal to allow the
MSL0 pin to stabilize prior to release of reset
(approximately 8µs per nF added).
The internal resistance of the POR pin is
approximately 5kΩ. This pin is not available in the
28-pin PLCC version.
- 6 -
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