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78M6613-IMR/F/PSU PDF预览

78M6613-IMR/F/PSU

更新时间: 2024-01-23 07:17:24
品牌 Logo 应用领域
TERIDIAN 闪存传感器
页数 文件大小 规格书
33页 742K
描述
Power Supply Management Circuit, Fixed, 1 Channel, 5 X 5 MM, ROHS COMPLIANT, QFN-32

78M6613-IMR/F/PSU 技术参数

是否无铅:含铅生命周期:Transferred
包装说明:5 X 5 MM, ROHS COMPLIANT, QFN-32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.67Is Samacsys:N
可调阈值:NO模拟集成电路 - 其他类型:POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码:S-XQCC-N32长度:5 mm
信道数量:1功能数量:1
端子数量:32最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
座面最大高度:0.9 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5 mmBase Number Matches:1

78M6613-IMR/F/PSU 数据手册

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78M6613 Data Sheet  
DS_6613_018  
1.3 Digital Computation Engine (CE)  
The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to  
accurately measure energy. The CE calculations and processes include:  
Multiplication of each current sample with its associated voltage sample to obtain the energy per  
sample (when multiplied with the constant sample time).  
Frequency-insensitive delay cancellation on all channels (to compensate for the delay between  
samples caused by the multiplexing scheme).  
90° phase shifter (for narrowband VARh calculations).  
Monitoring of the input signal frequency (for frequency and phase information).  
Monitoring of the input signal amplitude (for sag detection).  
Scaling of the processed samples based on calibration coefficients.  
CE code is provided by Teridian as a part of the application firmware available. The CE is not  
programmable by the user. Measurement algorithms in the CE code can be customized by  
Teridian upon request.  
The CE program resides in Flash memory. Common access to Flash memory by CE and MPU is  
controlled by a memory share circuit. Allocated Flash space for the CE program cannot exceed 1024  
words (2KB).  
The CE DRAM can be accessed by the CE and the MPU. Holding registers are used to convert 8-bit  
wide MPU data to/from 32-bit wide CE DRAM data, and wait states are inserted as needed, depending  
on the frequency of CKMPU. The CE DRAM contains 128 32-bit words. The MPU can read and write  
the CE DRAM as the primary means of data communication between the two processors. CE hardware  
issues an interrupt when accumulation is complete.  
1.4 80515 MPU Core  
The 78M6613 includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one  
clock cycle. Using a 5 MHz (4.9152 MHz) clock results in a processing throughput of 5 MIPS. The  
80515 architecture eliminates redundant bus states and implements parallel execution of fetch and  
execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most of the  
1-byte instructions are performed in a single cycle. This leads to an 8x performance (in average)  
improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency. Actual  
processor clocking speed can be adjusted to the total processing demand of the application  
(measurement calculations, memory management and I/O management).  
Typical power and energy measurement functions based on the results provided by the internal  
32-bit compute engine (CE) are available for the MPU as part of Teridian’s standard library.  
MPU Memory Organization, Special Function Registers, Interrupts, Counters, and other controls  
are described in the applicable firmware documentation.  
1.4.1 UART  
The 78M6613 includes a UART that can be programmed to communicate with a variety of external  
devices. The UART is a dedicated 2-wire serial interface, which can communicate with an external  
device at up to 38,400 bits/s. All UART transfers are programmable for parity enable, parity, 2 stop  
bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38,400 bps.  
8
Rev. 1.1  
 
 
 

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