Datasheet > 768141562JPTR

768141562JPTR

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
西迪斯 - CTS		/
页数	文件大小	规格书
5页	148K
描述
Leaded Surface Mount

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数据手册

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768141562JPTR 数据手册

Types of Circuits

Bussed (Schematic 1)

Isolated (Schematic 3)

Dual Terminator (Schematic 5)

R/2R Ladder (Schematic 7)

A DIM.

+.050

.200

-.030

"A" Dimension

.008 ^+.002

No. of Pins

-.001

in.

7.620

.300

5.590 ^+.130

.220

9.91 ±0.25

11.18 ±0.25

13.70 ±0.25

Notes

0.390 ±0.010

0.440 ±0.010

0.540 ±0.010

.810 ^+.330

-.250

+.005

-.010

PART NO.

DATE CODE

-.300

.032^+.013

-.012

MODULES WILL BE

MARKED WITH A SQUARE

AT PIN #1 (TOP MARKING)

0°- 8°

INSULATION COATING

APPLIED ON TWO SURFACES

BELOW

SEATING

PLANE

mm 0.10 MAX

in. 0.004

1.350

.053

1. Lead COPLANARITY

General Tolerances

1.600±.200

.063±.008

MAX. TYP.

.190±.060

.0075±.005

mm ±0.25

in. ±0.010

NOTE #1

.430±.050

.017±.002

1.270

TYP.

.050

mm & in. DIMENSIONS ARE NOT EQUIVALENT

Land Patterns

LEAD COUNT

in.

5.34

0.21

5.34

0.21

5.34

0.21

7.37

0.29

7.37

0.29

7.37

0.29

9.40

0.37

9.40

0.37

9.40

0.37

7.60

0.30

8.90

0.35

11.40

0.45

0.63

TYP.

.025

14P

16P

20P

in.

1.27

TYP.

.050

2.03

.080

TYP.

Page 2 of 5

January 2008

CTS Electronic Components

Leaded Surface Mount Series 768

www.ctscorp.com

123 4 5

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