ICL7660S
enough to fully charge the capacitors every cycle. In a typical
application where f = 10kHz and C = C = C = 10µF:
Changing the ICL7660S Oscillator Frequency
OSC
1
2
It may be desirable in some applications, due to noise or other
considerations, to alter the oscillator frequency. This can be
achieved simply by one of several methods described below.
1
+ 4 x ESR
+
C1
ESR
R
2 x 23 +
3
-6
O
(5 x 10 x 10 x 10
)
C2
R
46 + 20 + 5 x ESR Ω
C
By connecting the Boost Pin (Pin 1) to V+, the oscillator
O
charge and discharge current is increased and, hence, the
1
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
oscillator frequency is increased by approximately 3 /
2
times. The result is a decrease in the output impedance and
ripple. This is of major importance for surface mount
applications where capacitor size and cost are critical.
Smaller capacitors, e.g. 0.1µF, can be used in conjunction
with the Boost Pin in order to achieve similar output currents
compared to the device free running with C = C = 10µF or
potentially swamp out a low 1/f
x C ) term, rendering
PUMP
1
an increase in switching frequency or filter capacitance
ineffective. Typical electrolytic capacitors may have ESRs as
high as 10Ω.
Output Ripple
1
2
100µF. (Refer to graph of Output Source Resistance as a
Function of Oscillator Frequency).
ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2 voltages, A and B, as shown in
Figure 15. Segment A is the voltage drop across the ESR of
C at the instant it goes from being charged by C (current
Increasing the oscillator frequency can also be achieved by
overdriving the oscillator from an external clock, as shown in
Figure 18. In order to prevent device latchup, a 1kΩ resistor
must be used in series with the clock output. In a situation
where the designer has generated the external clock
frequency using TTL logic, the addition of a 10kΩ pullup
resistor to V+ supply is required. Note that the pump
2
1
flowing into C ) to being discharged through the load
2
(current flowing out of C ). The magnitude of this current
2
change is 2 x I
, hence the total drop is 2 x I
x
OUT
OUT
ESR V. Segment B is the voltage change across C during
C2
2
time t , the half of the cycle when C supplies current the
2
2
load. The drop at B is I
voltage is the sum of these voltage drops:
x t /C V. The peak-to-peak ripple
frequency with external clocking, as with internal clocking,
1
OUT
2
2
will be / of the clock frequency. Output transitions occur on
2
the positive going edge of the clock.
V
1
------------------------------------------- + 2 ESRC × I
RIPPLE
2
OUT
2 × f
PUMP × C
V+
V+
2
Again, a low ESR capacitor will result in a higher
performance output.
1
2
3
4
8
7
6
5
1kΩ
CMOS
GATE
ICL7660S
+
Paralleling Devices
10µF
-
Any number of ICL7660S voltage converters may be
paralleled to reduce output resistance. The reservoir
V
OUT
-
+
10µF
capacitor, C , serves all devices while each device requires
2
its own pump capacitor, C . The resultant output resistance
would be approximately:
1
FIGURE 15. EXTERNAL CLOCKING
It is also possible to increase the conversion efficiency of the
ICL7660S at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is shown
in Figure 19. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the
R
(of ICL7660S)
OUT
R
=
OUT
n (number of devices)
Cascading Devices
The ICL7660S may be cascaded as shown to produce larger
negative multiplication of the initial supply voltage. However,
due to the finite efficiency of each device, the practical limit is
10 devices for light loads. The output voltage is defined by:
pump (C ) and reservoir (C ) capacitors; this is overcome by
1
2
increasing the values of C and C by the same factor that
1
2
the frequency has been reduced. For example, the addition
of a 100pF capacitor between pin 7 (OSC and V+ will lower
the oscillator frequency to 1kHz from its nominal frequency
of 10kHz (a multiple of 10), and thereby necessitate
V
= -n(V ),
IN
OUT
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual ICL7660S
corresponding increase in the value of C and C (from
1
2
10µF to 100µF).
R
values.
OUT
3-42
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