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74VMEH22501ADGGRG4 PDF预览

74VMEH22501ADGGRG4

更新时间： 2024-01-24 03:08:00
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
31页 935K
描述
74V SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-48

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74VMEH22501ADGGRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP48,.3,20针数：48
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.37其他特性：TWO 1-BIT TRANSCEIVERS ALSO AVAILABLE
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
系列：74VJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：12.5 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.012 A
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：30 mA
Prop。Delay @ Nom-Sup：14.5 ns传播延迟（tpd）：10.1 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.45 V
最小供电电压 (Vsup)：3.15 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：6.1 mm
Base Number Matches：1

74VMEH22501ADGGRG4 数据手册

 浏览型号74VMEH22501ADGGRG4的Datasheet PDF文件第1页浏览型号74VMEH22501ADGGRG4的Datasheet PDF文件第2页浏览型号74VMEH22501ADGGRG4的Datasheet PDF文件第3页浏览型号74VMEH22501ADGGRG4的Datasheet PDF文件第5页浏览型号74VMEH22501ADGGRG4的Datasheet PDF文件第6页浏览型号74VMEH22501ADGGRG4的Datasheet PDF文件第7页 
SN74VMEH22501A  
SCES3620A –DECEMBER 2004–REVISED FEBRUARY 2010  
www.ti.com  
FUNCTIONAL DESCRIPTION  
The SN74VMEH22501A is a high-drive (–48/64 mA), 8-bit UBT transceiver containing D-type latches and D-type  
flip-flops for data-path operation in transparent, latched, or flip-flop modes. Data transmission is true logic. The  
device is uniquely partitioned as 8-bit UBT transceivers with two integrated 1-bit three-wire bus transceivers.  
Functional Description for Two 1-Bit Bus Transceivers  
The OEAB inputs control the activity of the 1B or 2B port. When OEAB is high, the B-port outputs are active.  
When OEAB is low, the B-port outputs are disabled.  
Separate 1A and 2A inputs and 1Y and 2Y outputs provide a feedback path for control and diagnostics  
monitoring. The OEBY inputs control the 1Y or 2Y outputs. When OEBY is low, the Y outputs are active. When  
OEBY is high, the Y outputs are disabled.  
The OEBY and OEAB inputs can be tied together to form a simple direction control where an input high yields  
A data to B bus and an input low yields B data to Y bus.  
1-BIT BUS TRANSCEIVER FUNCTION TABLE  
INPUTS  
OUTPUT  
MODE  
Isolation  
OEAB  
OEBY  
L
H
L
H
H
L
Z
A data to B bus  
True driver  
B data to Y bus  
H
L
A data to B bus, B data to Y bus  
True driver with feedback path  
Functional Description for 8-Bit UBT Transceiver  
The 3A and 3B data flow in each direction is controlled by the OE and direction-control (DIR) inputs. When OE is  
low, all 3A- or 3B-port outputs are active. When OE is high, all 3A- or 3B-port outputs are in the high-impedance  
state.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
OE DIR  
H
L
L
X
H
L
Z
3A data to 3B bus  
3B data to 3A bus  
The UBT transceiver functions are controlled by latch-enable (LE) and clock (CLKAB and CLKBA) inputs. For  
3A-to-3B data flow, the UBT operates in the transparent mode when LE is high. When LE is low, the 3A data is  
latched if CLKAB is held at a high or low logic level. If LE is low, the 3A data is stored in the latch/flip-flop on the  
low-to-high transition of CLKAB.  
The UBT transceiver data flow for 3B to 3A is similar to that of 3A to 3B, but uses CLKBA.  
4
Submit Documentation Feedback  
Copyright © 2004–2010, Texas Instruments Incorporated  
Product Folder Link(s): SN74VMEH22501A  
1234567...31

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