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74VHC164MX PDF预览

74VHC164MX

更新时间: 2024-02-11 12:34:56
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
11页 992K
描述
AHC/VHC/H/U/V SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO14, 0.150 INCH, LEAD FREE, MS-012AB, SOIC-14

74VHC164MX 技术参数

是否无铅: 不含铅生命周期:Active
包装说明:SOP, SOP14,.25Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:0.72
计数方向:RIGHT系列:AHC/VHC/H/U/V
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.625 mm负载电容(CL):50 pF
逻辑集成电路类型:SERIAL IN PARALLEL OUT最大频率@ Nom-Sup:45000000 Hz
湿度敏感等级:1位数:8
功能数量:1端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/5.5 V
传播延迟(tpd):18.5 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Shift Registers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:105 MHz

74VHC164MX 数据手册

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Connection Diagram  
Logic Symbol  
Function Table  
Pin Description  
Operating  
Mode  
Inputs  
Outputs  
Pin  
Names  
Description  
MR  
A
X
L
B
X
L
Q
Q –Q  
0
1
7
Reset (Clear)  
Shift  
L
L
L
L
L
H
L–L  
A, B  
Data Inputs  
H
H
H
H
Q –Q  
0 6  
CP  
Clock Pulse Input (Active Rising Edge)  
Master Reset Input (Active LOW)  
Outputs  
L
H
L
Q –Q  
0
6
6
6
MR  
H
H
Q –Q  
0
Q –Q  
0
7
H
Q –Q  
0
H = HIGH Voltage Levels  
L = LOW Voltage Levels  
X = Immaterial  
Functional Description  
The VHC164 is an edge-triggered 8-bit shift register with  
serial data entry and an output from each of the eight  
stages. Data is entered serially through one of two inputs  
(A or B); either of these inputs can be used as an active  
High Enable for data entry through the other input. An  
unused input must be tied HIGH.  
Q = Lower case letters indicate the state of the  
referenced input or output one setup time prior to  
the LOW-to-HIGH clock transition.  
Each LOW-to-HIGH transition on the Clock (CP) input  
shifts data one place to the right and enters into Q the  
0
logical AND of the two data inputs (A • B) that existed  
before the rising clock edge. A LOW level on the Master  
Reset (MR) input overrides all other inputs and clears  
the register asynchronously, forcing all Q outputs LOW.  
Logic Diagram  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to  
estimate propagation delays.  
©1993 Fairchild Semiconductor Corporation  
74VHC164 Rev. 1.4.0  
www.fairchildsemi.com  
2

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