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74VHC163SJX PDF预览

74VHC163SJX

更新时间： 2024-02-19 15:39:00
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 125K
描述
COUNTER|UP|4-BIT BINARY|HC-CMOS|SOP|16PIN|PLASTIC

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74VHC163SJX 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：5.30 MM, EIAJ TYPE2, SOP-16
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.71
计数方向：UP系列：AHC/VHC
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：10.2 mm负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：50000000 Hz最大I（ol）：0.004 A
工作模式：SYNCHRONOUS湿度敏感等级：1
位数：4功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：2/5.5 V
传播延迟（tpd）：18.5 ns认证状态：Not Qualified
座面最大高度：2.1 mm子类别：Counters
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：5.3 mm最小 fmax：115 MHz
Base Number Matches：1

74VHC163SJX 数据手册

 浏览型号74VHC163SJX的Datasheet PDF文件第1页浏览型号74VHC163SJX的Datasheet PDF文件第3页浏览型号74VHC163SJX的Datasheet PDF文件第4页浏览型号74VHC163SJX的Datasheet PDF文件第5页浏览型号74VHC163SJX的Datasheet PDF文件第6页浏览型号74VHC163SJX的Datasheet PDF文件第7页 
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
CEP  
CET  
CP  
Count Enable Parallel Input  
Count Enable Trickle Input  
Clock Pulse Input  
MR  
Synchronous Master Reset Input  
Parallel Data Inputs  
P0–P3  
PE  
Parallel Enable Inputs  
Flip-Flop Outputs  
Q0–Q3  
TC  
Terminal Count Output  
Functional Description  
The VHC163 counts in modulo-16 binary sequence. From  
state 15 (HHHH) it increments to state 0 (LLLL). The clock  
inputs of all flip-flops are driven in parallel through a clock  
buffer. Thus all changes of the Q outputs occur as a result  
of, and synchronous with, the LOW-to-HIGH transition of  
the CP input signal. The circuits have four fundamental  
modes of operation, in order of precedence: synchronous  
reset, parallel load, count-up and hold. Four control  
inputs—Synchronous Reset (MR), Parallel Enable (PE),  
Count Enable Parallel (CEP) and Count Enable Trickle  
(CET)—determine the mode of operation, as shown in the  
Mode Select Table. A LOW signal on MR overrides count-  
ing and parallel loading and allows all outputs to go LOW  
on the next rising edge of CP. A LOW signal on PE over-  
rides counting and allows information on the Parallel Data  
(Pn) inputs to be loaded into the flip-flops on the next rising  
The Terminal Count (TC) output is HIGH when CET is  
HIGH and counter is in state 15. To implement synchro-  
nous multistage counters, the TC outputs can be used with  
the CEP and CET inputs in two different ways.  
Figure 1 shows the connections for simple ripple carry, in  
which the clock period must be longer than the CP to TC  
delay of the first stage, plus the cumulative CET to TC  
delays of the intermediate stages, plus the CET to CP  
setup time of the last stage. This total delay plus setup time  
sets the upper limit on clock frequency. For faster clock  
rates, the carry lookahead connections shown in Figure 2  
are recommended. In this scheme the ripple delay through  
the intermediate stages commences with the same clock  
that causes the first stage to tick over from max to min to  
start its final cycle. Since this final cycle takes 16 clocks to  
complete, there is plenty of time for the ripple to progress  
through the intermediate stages. The critical timing that lim-  
its the clock period is the CP to TC delay of the first stage  
plus the CEP to CP setup time of the last stage. The TC  
output is subject to decoding spikes due to internal race  
conditions and is therefore not recommended for use as a  
clock or asynchronous reset for flip-flops, registers or  
counters.  
edge of CP. With PE and MR HIGH, CEP and CET permit  
counting when both are HIGH. Conversely, a LOW signal  
on either CEP or CET inhibits counting.  
The VHC163 uses D-type edge-triggered flip-flops and  
changing the MR, PE, CEP and CET inputs when the CP is  
in either state does not cause errors, provided that the rec-  
ommended setup and hold times, with respect to the rising  
edge of CP, are observed.  
Logic Equations: Count Enable = CEP • CET • PE  
TC = Q0 • Q1 • Q 2 • Q3 • CET  
FIGURE 1.  
FIGURE 2.  
www.fairchildsemi.com  
2
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