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74LVCE161284VRG4 PDF预览

74LVCE161284VRG4

更新时间: 2024-02-03 08:13:36
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路电视光电二极管
页数 文件大小 规格书
16页 366K
描述
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP

74LVCE161284VRG4 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:GREEN, PLASTIC, TVSOP-48针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.67
Is Samacsys:N差分输出:NO
驱动器位数:14输入特性:STANDARD
接口集成电路类型:LINE TRANSCEIVER接口标准:IEEE-1284
JESD-30 代码:R-PDSO-G48JESD-609代码:e4
长度:9.7 mm湿度敏感等级:1
功能数量:13端子数量:48
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
最大接收延迟:18 ns接收器位数:13
座面最大高度:1.2 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.4 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED最大传输延迟:30 ns
宽度:4.4 mmBase Number Matches:1

74LVCE161284VRG4 数据手册

 浏览型号74LVCE161284VRG4的Datasheet PDF文件第4页浏览型号74LVCE161284VRG4的Datasheet PDF文件第5页浏览型号74LVCE161284VRG4的Datasheet PDF文件第6页浏览型号74LVCE161284VRG4的Datasheet PDF文件第8页浏览型号74LVCE161284VRG4的Datasheet PDF文件第9页浏览型号74LVCE161284VRG4的Datasheet PDF文件第10页 
SN74LVCE161284  
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER  
WITH ERROR-FREE POWER UP  
www.ti.com  
SCES541JANUARY 2004REVISED MARCH 2005  
Switching Characteristics  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2 and  
Figure 3)  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
tPLH  
MIN TYP(1)  
MAX UNIT  
2
2
30  
ns  
30  
Totem pole  
Totem pole  
Totem pole  
Totem pole  
Totem pole  
A1–A8  
A9–A13  
B1–B8  
Y9–Y13  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tslew  
tPZH  
tPHZ  
ten–tdis  
tPHZ  
tPLZ  
2
30  
ns  
30  
2
2
12  
ns  
12  
B1–B8  
A1–A8  
2
2
14  
ns  
14  
C14–C17  
A14–A17  
2
2
16  
ns  
16  
PERI LOGIC IN  
HOST LOGIC IN  
PERI LOGIC OUT  
HOST LOGIC OUT  
2
1
18  
ns  
18  
Totem pole  
Totem pole  
1
B1–B8 and Y9–Y13 outputs  
0.05  
2
0.4  
30  
V/ns  
B1–B8, Y9–Y13, and  
PERI LOGIC OUT  
HD  
DIR  
DIR  
ns  
2
25  
A1–A8  
B1–B8  
2
25  
ns  
2
25  
ns  
2
25  
tr, tf  
Open drain  
A1–A13  
B1–B8 or Y9–Y13  
B1–B8 or A1–A8  
1
120  
10  
ns  
ns  
(2)  
tsk(o)  
A1–A8 or B1–B8  
3
(1) Typical values are measured at VCC = 3.3 V, VCC CABLE = 5 V, and TA = 25°C.  
(2) Skew is measured at 1/2 (VOH + VOL) for signals switching in the same direction.  
Table 1. ESD Protection  
PIN  
TEST CONDITIONS  
TYP UNIT  
HBM  
±15  
B1–B8, Y9–Y13, PERI LOGIC OUT,  
C14–C17, HOST LOGIC IN  
Contact discharge, IEC 61000-4-2  
Air-gap discharge, IEC 61000-4-2  
±8  
kV  
kV  
±15  
DIR, HD, A1–A8, A9–A13,  
PERI LOGIC IN, A14–A17,  
HOST LOGIC OUT  
HBM  
±4  
Operating Characteristics  
VCC and VCC CABLE = 3.3 V, CL = 0, f = 10 MHz, TA = 25°C  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
TYP UNIT  
A
B
15  
6
A
Y
PERI LOGIC IN  
PERI LOGIC OUT  
10  
pF  
33  
Cpd  
Power dissipation capacitance  
B
A
C
A
29  
29  
HOST LOGIC IN  
HOST LOGIC OUT  
7

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