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74HCT573PW-T PDF预览

74HCT573PW-T

更新时间: 2024-01-30 16:07:44
品牌 Logo 应用领域
恩智浦 - NXP 锁存器
页数 文件大小 规格书
7页 65K
描述
HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-20

74HCT573PW-T 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.06其他特性:BROADSIDE VERSION OF 373
系列:HCTJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):53 ns认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

74HCT573PW-T 数据手册

 浏览型号74HCT573PW-T的Datasheet PDF文件第1页浏览型号74HCT573PW-T的Datasheet PDF文件第2页浏览型号74HCT573PW-T的Datasheet PDF文件第3页浏览型号74HCT573PW-T的Datasheet PDF文件第4页浏览型号74HCT573PW-T的Datasheet PDF文件第5页浏览型号74HCT573PW-T的Datasheet PDF文件第6页 
Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74HC/HCT573  
AC WAVEFORMS  
(1) HC : VM = 50%; VI = GND to VCC  
.
(1) HC : VM = 50%; VI = GND to VCC  
.
HCT: VM = 1.3 V; VI = GND to 3 V.  
HCT: VM = 1.3 V; VI = GND to 3 V.  
Fig.7 Waveforms showing the latch enable input  
(LE) pulse width, the latch enable input to  
output (Qn) propagation delays and the  
output transition times.  
Fig.6 Waveforms showing the data input (Dn) to  
output (Qn) propagation delays and the  
output transition times.  
The shaded areas indicate when the input is permitted to  
change for predictable output performance.  
(1) HC : VM = 50%; VI = GND to VCC  
.
HCT: VM = 1.3 V; VI = GND to 3 V.  
Fig.9 Waveforms showing the data set-up and  
hold times for Dn input to LE input.  
(1) HC : VM = 50%; VI = GND to VCC  
.
HCT: VM = 1.3 V; VI = GND to 3 V.  
PACKAGE OUTLINES  
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.  
Fig.8 Waveforms showing the 3-state enable and  
disable times.  
December 1990  
7

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