Datasheet > 74HC670D,653

74HC670D,653

更新时间： 2024-01-26 18:22:35

品牌	Logo	应用领域
恩智浦 - NXP		静态存储器光电二极管内存集成电路
页数	文件大小	规格书
9页	79K
描述
4X4 STANDARD SRAM, 59ns, PDSO16

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74HC670D,653 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	包装说明：	SOP,
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.57	最长访问时间：	59 ns
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e4
长度：	9.9 mm	内存密度：	16 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	4
湿度敏感等级：	1	功能数量：	1
端口数量：	1	端子数量：	16
字数：	4 words	字数代码：	4
工作模式：	ASYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-40 °C	组织：	4X4
输出特性：	3-STATE	可输出：	NO
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	1.75 mm
最大供电电压 (Vsup)：	6 V	最小供电电压 (Vsup)：	2 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	AUTOMOTIVE
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	3.9 mm
Base Number Matches：	1

74HC670D,653 数据手册

Philips Semiconductors

Product speciﬁcation

4 x 4 register ﬁle; 3-state

74HC/HCT670

the location of the stored word. When the WE input is

LOW, the data is entered into the addressed location. The

addressed location remains transparent to the data while

the WE input is LOW. Data supplied at the inputs will be

read out in true (non-inverting) form from the 3-state

outputs (Q₀to Q₃). D_nand W_ninputs are inhibited when

WE is HIGH.

FEATURES

• Simultaneous and independent read and write

operations

• Expandable to almost any word size and bit length

• Output capability: bus driver

• I_CCcategory: MSI

Direct acquisition of data stored in any of the four registers

is made possible by individual read address inputs

(R_Aand R_B). The addressed word appears at the four

outputs when the RE is LOW. Data outputs are in the high

impedance OFF-state when RE is HIGH. This permits

outputs to be tied together to increase the word capacity to

very large numbers.

GENERAL DESCRIPTION

The 74HC/HCT670 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT670 are 16-bit 3-state register files

Design of the read enable signals for the stacked devices

must ensure that there is no overlap in the LOW levels

which would cause more than one output to be active at

the same time. Parallel expansion to generate n-bit words

is accomplished by driving the enable and address inputs

of each device in parallel.

organized as 4 words of 4 bits each. Separated read and

write address inputs (R_A, R_Band W_A, W_B) and enable

inputs (RE and WE) are available, permitting simultaneous

writing into one word location and reading from another

location. The 4-bit word to be stored is presented to four

data inputs (D₀to D₃). The W_Aand W_Binputs determine

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

TYPICAL

SYMBOL PARAMETER

CONDITIONS

UNIT

HCT

t_PHL/ t_PLHpropagation delay D_nto Q_n

C_L= 15 pF; V_CC= 5 V

C_I

input capacitance

3.5

C_PD

power dissipation capacitance per package

notes 1 and 2

122

124

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC× f_o)

where:

f_i= input frequency in MHz

f_o= output frequency in MHz

∑ (C_L× V_CC× f_o) = sum of outputs

C_L= output load capacitance in pF

V_CC= supply voltage in V

2. For HC the condition is V_I= GND to V_CC

;

for HCT the condition is V_I= GND to V_CC−1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

123 4 5 6 7...9

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与74HC670D,653相关器件

型号	品牌	描述	获取价格	数据表
74HC670D/T3	NXP	4X4 STANDARD SRAM, 59ns, PDSO16, SOP-16	获取价格
74HC670DB	NXP	IC 4 X 4 STANDARD SRAM, 59 ns, PDSO16, Static RAM	获取价格
74HC670DB,112	NXP	IC 4 X 4 STANDARD SRAM, 59 ns, PDSO16, Static RAM	获取价格
74HC670DB,118	NXP	IC 4 X 4 STANDARD SRAM, 59 ns, PDSO16, Static RAM	获取价格
74HC670DB-T	NXP	暂无描述	获取价格
74HC670D-T	ETC	Register File	获取价格

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