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74HC564N,652 PDF预览

74HC564N,652

更新时间: 2024-02-06 11:03:45
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管逻辑集成电路触发器
页数 文件大小 规格书
18页 96K
描述
74HC564 - Octal D-type flip-flop; positive-edge trigger; 3-state; inverting DIP 20-Pin

74HC564N,652 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP20,.3
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:8.24
其他特性:BROADSIDE VERSION OF 534系列:HC/UH
JESD-30 代码:R-PDIP-T20JESD-609代码:e4
长度:26.73 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:24000000 Hz
最大I(ol):0.006 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):260电源:2/6 V
传播延迟(tpd):250 ns认证状态:Not Qualified
座面最大高度:4.2 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:7.62 mmBase Number Matches:1

74HC564N,652 数据手册

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74HC564  
Octal D-type flip-flop; positive-edge trigger; 3-state; inverting  
Rev. 03 — 11 November 2004  
Product data sheet  
1. General description  
The 74HC564 is a high-speed Si-gate CMOS device and is pin compatible with low-power  
Schottky TTL (LSTTL). The 74HC564 is specified in compliance with JEDEC  
standard no. 7A.  
The 74HC564 is a octal D-type flip-flop featuring separate D-type inputs for each flip-flop  
and inverting 3-state outputs for bus oriented applications. A clock (CP) and an output  
enable (OE) input are common to all flip-flops.  
The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold  
times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of  
the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the  
high-impedance OFF-state. Operation of the OE input does not affect the state of the  
flip-flops.  
The 74HC564 is functionally identical to the 74HC574 but has inverting outputs. The  
74HC564 is functionally identical to the 74HC534, but has a different pinning.  
2. Features  
3-state inverting outputs for bus oriented applications  
8-bit positive-edge triggered register  
Common 3-state output enable input  
Independent register and 3-state buffer operation  
Low-power dissipation  
Complies with JEDEC standard no. 7A  
ESD protection:  
HBM EIA/JESD22-A114-B exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
Multiple package options  
Specified from 40 °C to +80 °C and from 40 °C to +125 °C.  
 
 

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