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74HC573PW PDF预览

74HC573PW

更新时间: 2024-11-20 11:10:31
品牌 Logo 应用领域
安世 - NEXPERIA PC驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 274K
描述
Octal D-type transparent latch; 3-stateProduction

74HC573PW 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP-20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.56
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:4911Samacsys Pin Count:20
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Small Outline Packages
Samacsys Footprint Name:SOT360-1Samacsys Released Date:2015-04-16 09:48:08
Is Samacsys:N系列:HC/UH
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):225 ns座面最大高度:1.1 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

74HC573PW 数据手册

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74HC573; 74HCT573  
Octal D-type transparent latch; 3-state  
Rev. 8 — 10 September 2021  
Product data sheet  
1. General description  
The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device  
features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs  
enter the latches. In this condition the latches are transparent, a latch output will change each time  
its corresponding D-input changes. When LE is LOW the latches store the information that was  
present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE  
causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not  
affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting  
resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Wide supply voltage range from 2.0 to 6.0 V  
CMOS low power dissipation  
High noise immunity  
Input levels:  
For 74HC573: CMOS level  
For 74HCT573: TTL level  
Inputs and outputs on opposite sides of package allowing easy interface with microprocessors  
Useful as input or output port for microprocessors and microcomputers  
3-state non-inverting outputs for bus-oriented applications  
Common 3-state output enable input  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Complies with JEDEC standards:  
JESD8C (2.7 V to 3.6 V)  
JESD7A (2.0 V to 6.0 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74HC573D  
-40 °C to +125 °C  
-40 °C to +125 °C  
-40 °C to +125 °C  
SO20  
plastic small outline package; 20 leads;  
body width 7.5 mm  
SOT163-1  
74HCT573D  
74HC573PW  
74HCT573PW  
74HC573BQ  
74HCT573BQ  
TSSOP20  
plastic thin shrink small outline package; 20 leads;  
body width 4.4 mm  
SOT360-1  
SOT764-1  
DHVQFN20 plastic dual in-line compatible thermal enhanced  
very thin quad flat package; no leads; 20 terminals;  
body 2.5 × 4.5 × 0.85 mm  
 
 
 

74HC573PW 替代型号

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